Integrated Device Technology, Inc.

Renesas Electronics America Inc.

Synaptics Corporation

Shubing Zhai

Xiaoqian Zhang

Wei W Wang

James Wang

Yanbo Wang

Jankin Hu

Zhonghai Gan

Chenxiao Ren

David Chang

Sibing Wang

Fei Ma

Xudong Shi

Yefei Sun

Hanbing Jiang

Apparatuses for controlling data transaction between master and slave devices are described. A master port connected to a master device can include a voltage regulator, a bridging circuit connected to a network element, and a redriver circuit. In response to a data transaction corresponding to a first type of data transaction, the master port can activate the voltage regulator and deactivate the redriver circuit to support a first operation mode causing the master device to perform the data transaction with a slave device via the network element. In response to the data transaction corresponding to a second type of data transaction, the master port can deactivate the voltage regulator and activate the redriver circuit to support a second operation mode causing the master port to disconnect from a slave port connected to the slave device and the data transaction is fulfilled by a circuit connected to the slave device.

Network device configuration based on slave device type

Systems and methods for controlling data transaction between master and slave devices are described. A master device can be connected to multiple slave devices that can operate under one of a first, a second, and a third operation modes. The first operation mode can cause the master device to perform data transactions with the multiple slave devices via a network element and the multiple slave devices can be connected to one another via the network element. The second operation mode can disconnect the master device from the multiple slave devices, and multiple agents connected to the multiple slave devices can fulfill the data transactions. The third operation mode can cause the master device to perform data transactions with a first subset of the multiple slave devices via the network element, and can cause the master device to be disconnected from a second subset of the multiple slave devices.

An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

Resynchronization of a clock associated with each data bit in a double data rate memory system

A power management integrated circuit incorporates (a) a microprocessor; (b) a non-volatile memory accessible by the microprocessor for storing programs executable by the microprocessor; (c) a random access memory accessible by the microprocessor; (d) an external interface which allows an external device to communicate with the power management integrated circuit; and (e) power regulators providing regulated output voltages from the power management integrated circuit, each power regulator being controllable by the microprocessor and the external interface over the register-controlled bus. A second external interface may be provided, which is used to provide a configuration file descriptive of power requirements of a system in which the power management integrated circuit is deployed. Such a system may include a system-on-a-chip (SOC) integrated circuit. Initially, the microprocessor of the power management integrated circuit executes a power sequence to provide the power-up power supply voltages to the SOC integrated circuit. Thereafter, the SOC integrated circuit controls power-up sequences for the peripheral devices. The configuration file is derived from a script file that is editable by a text editor or a word processor. The script file may be based on a scripting language that allows specifying control of the power regulators of the power management integrated circuit.

Power management integrated circuit using a flexible script-based configurator and method for power management

The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

Stream clock recovery in high definition multimedia digital system

Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.

Method and apparatus for forwarding bursty data

A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

Phase-locked loop

A method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a System Packet Interface device have been disclosed.

Method and apparatus for generic interface, packet cut-through, overbooking, queue concatenation, and logical identification priority for a system packet interface device

A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal. The clock signal selector may include a plurality of clock signal selectors, respective ones of which receive the plurality of clock signals and selectively apply the plurality of clock signals to respective ones of the data output buffers responsive to the second control signal.

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Shanghai, China

Shubing Zhai