Changxin Memory Technologies, Inc.

Shuai Guo

Mingguang Zuo

Shijie Bai

A method for forming a semiconductor device includes: providing a substrate and a stacked structure covering the substrate and including alternately stacked dielectric layers and sacrificial layers; forming multiple isolation layers extending in a first direction and arranged in a second direction in the stacked structure, the first direction being perpendicular to the substrate surface and the second direction being perpendicular to the first direction; forming a bit line between two adjacent ones of the isolation layers and removing the sacrificial layers; forming capacitor via holes along a third direction at vacancies of the dielectric structure formed after removing the sacrificial layers, the third, first and second directions being perpendicular; forming transistors and capacitors sequentially in the capacitor via holes based on bit lines, the capacitors being parallel to the substrate surface; and forming a word line extending in the second direction between two adjacent ones of the transistors.

Method for forming semiconductor device and semiconductor device

The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a memory device, and a manufacturing method and a driving method thereof. The memory device includes: a substrate; a stacked structure, where the stacked structure includes a first gate layer, a second gate layer, and interlayer isolation layers, one of the interlayer isolation layers is located between the first gate layer and the second gate layer, and another one of the interlayer isolation layers is located between the first gate layer and the substrate; and a memory structure, including a through hole penetrating the stacked structure, and a trench structure filled in the through hole. The present disclosure enables the memory device to be used as nonvolatile memory with different storage modes, thereby realizing versatility of the memory device.

Memory device, and manufacturing method and driving method thereof

A semiconductor structure, a forming method thereof and a memory are provided. Wherein the semiconductor structure includes: a substrate; a bit line layer, located in the substrate; a word line stack layer, located on the substrate, wherein the word line stack layer includes a word line layer; and a gap, located between the bit line layer and the word line layer.

Semiconductor memory structure

Embodiments provide method for fabricating a semiconductor structure, and a semiconductor structure. The method includes: providing a substrate, a thin-film stack structure being formed on the substrate; forming a first groove and a second groove in the thin-film stack structure, and forming write transistors in the first groove, the second groove extending along a first direction, and the second groove being positioned between adjacent two of the write transistors in a second direction; removing a part of the thin-film stack structure by etching using the second groove to form a first hole and a second hole respectively, forming a write word line in the first hole, and forming a write bit line in the second hole; forming a first via on an upper surface of the thin-film stack structure, and forming a storage node in the first via; and forming a read transistor, a read bit line and a lead.

Method for fabricating semiconductor structure, semiconductor structure, and memory

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.

Manufacturing method of semiconductor structure and semiconductor structure

A method for adjusting wafer deformation and a semiconductor structure are provided. The method includes the following operations. A deformation position and a deformation degree of a wafer are determined. At least one groove is formed at a back of the wafer according to the deformation position and the deformation degree. A stress film having a stress effect on the wafer deformation is formed at the back of the wafer with the at least one groove, and the stress film covers an inner wall of the at least one groove.

Method for adjusting wafer deformation and semiconductor structure

The embodiment of the application provides a method of manufacturing a semiconductor structure, which comprises the following steps: forming a target layer, a first mask layer, an isolation layer and an intermediate layer sequentially on a substrate, wherein first trench is disposed in the intermediate layer in the first region and second trench is disposed in the intermediate layer in the second region; forming a fill layer, and the difference in the height between the top surface of the fill layer in the first region and in the second region is less than or equal to a first preset value; removing a portion of the fill layer in the first region until the top surface of the sacrificial layer is exposed; removing the sacrificial layer; and etching a portion of the target layer through the first opening, wherein the remaining target layer forms a target pattern.

Method for manufacturing semiconductor structure

The method for forming overlay marks includes: providing a substrate, a surface of the substrate having a mark layer and a first mask layer; forming first trenches and second trenches in the first mask layer; forming a spacer layer covering side walls of the first trenches and side walls of the second trenches; backfilling the first trenches and the second trenches; removing the spacer layer; and etching the mark layer and forming main overlay marks and dummy overlay marks.

Method for forming overlay marks and semiconductor structure

A method of manufacturing a semiconductor structure includes: providing a base and a dielectric layer on the base, the base in an array region being provided with discrete capacitive contact plugs and a first conductive layer being formed on a top surface of the capacitive contact plugs; sequentially forming a conversion layer and a target layer on the first conductive layer and the dielectric layer, the target layer in the array region and the first circuit region being provided with first openings through the target layer; patterning the target layer in the array region as well as in the first circuit region and the second circuit region to form a second opening and a third opening; etching the conversion layer to form a first trench; forming a filling layer filling the first trench and removing the conversion layer to form a second trench filled by a second conductive layer.

Method of manufacturing a semiconductor structure, and a semiconductor structure

A method for manufacturing a semiconductor structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to each other, and a transistor being arranged on the second surface; forming release holes in the substrate, the release holes extending into the transistors, bottoms of the release holes being located in channel regions of the transistors, and top surfaces of the release holes being flush with the first surface; and forming a conductive structure in the release holes.

Method for manufacturing semiconductor structure and semiconductor structure

Embodiments disclose a capacitor array structure and a method for fabricating a capacitor array structure. The method includes: after forming a first capacitor hole, providing a bonded wafer including a second substrate, a second supporting layer and a second sacrificial layer stacked in sequence, and bonding the bonded wafer to a stacked structure, wherein a surface of the second sacrificial layer away from the second supporting layer is a bonding surface; forming a second capacitor hole, the second capacitor hole penetrating into the bonded wafer at least along a thickness direction to expose the first capacitor hole, such that the first capacitor hole is connected with the second capacitor hole.

Capacitor array structure and fabrication method thereof

A memory device and a forming method thereof are provided. The memory device includes: a semiconductor substrate, wherein multiple active regions are formed in the semiconductor substrate, and the multiple active regions are separated by multiple first trenches extending along a first direction and multiple second trenches extending along a second direction; a third trench, extending along the first direction and located in the semiconductor substrate at the bottom of the first trench; a bit line doped region, located in the semiconductor substrate on two sides of the third trench; a gate dielectric layer, located on a sidewall surface of the first trench and a sidewall surface of the second trench; a first dielectric layer that fills the third trench; a metal gate, located in the second trench and the first trench on the first dielectric layer.

Memory device and forming method thereof

A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a semiconductor substrate, and forming a first bit line; forming a support layer on the semiconductor substrate, the support layer including a first oxide layer, a first sacrificial layer, a second oxide layer, a second sacrificial layer, a third oxide layer, a third sacrificial layer and a fourth oxide layer that are stacked; forming, at a position corresponding to the first bit line, an active pillar penetrating through the support layer; removing each of the first sacrificial layer and the third sacrificial layer, and forming a first trench; removing a peripheral wall of the active pillar to form a first annular groove, a size of the first annular groove being greater than a size of the first trench in a vertical direction; forming a P-type filler in the first annular groove.

Method of manufacturing semiconductor structure and semiconductor structure

The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of laminated structures arranged at intervals on the substrate, the laminated structure includes a first conductive layer, an insulating layer, and a second conductive layer, and at least one of the first conductive layer and the second conductive layer is a semi-metal layer; forming a channel layer covering the laminated structures, and a dielectric layer covering the channel layer; and forming word lines (WLs) extending along a first direction, the WL includes a plurality of contact parts and a connecting part connecting adjacent contact parts, the contact part surrounds and is in contact with a side surface of the dielectric layer, and the contact part is opposite to at least a part of the insulating layer.

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Hefei, China

Shuai Guo