Csmc Technologies Fab1 Co., Ltd.

Csmc Technologies Fab2 Co., Ltd.

Shu Zhang

Junpan Guo

Le Wang

Shilin Fang

Faye Lu

Jianmei Xu

Zhengpei Chen

Yanqiang He

Guipeng Sun

Guangtao Han

Tse-Huang Lo

Hsiao-Chia Wu

Zehuang Luo

TseHuang Lo

Xiaojia Wu

HsiaoChia Wu

Hsiaochia Wu

Jian Xu

Tsehuang Lo

Min He

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Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S); coating a photoresist on the surface of the wafer (S); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S); performing ion implantation via the first implantation window to form a drift region in the substrate (S); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S); and etching the oxide layer to form the oxide layer of the drift region (S). Further provided is a laterally diffused metal oxide semiconductor device.

Laterally diffused metal oxide semiconductor device and manufacturing method therefor

Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Power MOS device structure

A manufacturing method for a semiconductor device with a discrete field oxide structure is provided, the method includes: growing a first PAD oxide layer on the surface of a wafer; forming a first silicon nitride layer () on the first PAD oxide layer through deposition; defining a field region by photolithography and etching same to remove the first silicon nitride layer () located on the field region; performing an ion implantation process to the field region; performing field region oxidation to grow a field oxide layer (); peeling off the first silicon nitride layer (); wet-dipping the wafer to remove the first PAD oxide layer and a part of field oxide layer (); growing a second PAD oxide layer on the surface of the wafer, and forming a second silicon nitride layer () on the second PAD oxide layer through deposition; defining a drift region by photolithography and etching same to remove the second silicon nitride layer () on the drift region; performing an ion implantation process to the drift region; and performing drift region oxidation to grow a drift region oxide layer (). The above-mentioned method peels off the silicon nitride layer () after the growth of the field oxide layer () is finished, at this time, the length of a bird beak of field-oxide () can be optimized by adjusting a wet-dipping amount to solve the problem that the bird beak of field-oxide () is too long.

Manufacturing method for semiconductor device with discrete field oxide structure

A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti&#x2014;TiN laminated structure is used as an anti-reflection layer to implement 4 &#x3bc;m metal etching without residue. In the metal patterning step, Nis used for the protection of a sidewall to implement on a 4 &#x3bc;m metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 &#x3bc;m metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 &#x3bc;m thick metal structure having a linewidth/gap of 1.5 &#x3bc;m/1.5 &#x3bc;m is finally implemented.

Method for manufacturing semiconductor thick metal structure

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Jiangsu, China

Shu Zhang