Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu-Yu Chen

Clement Hsingjen Wann

Chih-Sheng Chang

Yi-Tang Lin

Chien-Wen Chen

Cheok-Kei Lei

Hsiao-Hui Chen

Yu-Ning Chang

Sheng-Hsiung Chen

Wen-Hao Chen

Yu-Ti Su

Chun-Chen Chen

Shao-Huan Wang

Wan-Yen Lin

Ming-Huei Tsai

The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.

Must-join pin sign-off method

A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.

System for and method of designing an integrated circuit

A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.

System and methods for converting planar design to FinFET design

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

Growing community of inventors

Hsinchu, Taiwan

Shu-Yu Chen