Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu Yi Ying

Chung-Hsing Wang

Chih Sheng Tsai

Lee-Chung Lu

Yi-Kan Cheng

Hsiao-Shu Chao

Ho Che Yu

Chin-Yu Chiang

Fu-Lung Hsueh

Chih-Chieh Chen

Wei-Pin Changchein

Chen-Fu Huang

Chen-Fu “Alex” Huang

An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

Optimization for circuit migration

An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.

Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Clock circuit and method for pulsed latch circuits

Circuit and methods for automatic clock skew compensation in circuits having two power domains. When one of the power domains is operated with a lowered supply voltage, lowering the supply voltage tends to slow the clock pulse and produces clock skew. Circuitry is provided for selectively delaying the clock pulse in one of the power domains to reduce the clock skew by comparing the clock pulses, and then automatically delaying the clock pulse in one of the domains by a delay determined to minimize the skew. A method is provided where the clock skew between two clock pulses is determined and the delay needed in one of the clock pulses to reduce the skew is determined by sampling the clock skew using a plurality of delays at multiples of a minimum delay, and then automatically delaying the one clock pulse by selecting an appropriate delay. The method may be iterated.

Circuit and method for clock skew compensation in voltage scaling

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Taichung, Taiwan

Shu Yi Ying