United Semiconductor Corp.

United Microelectronics Corp.

Shu-Ya Chuang

Anchor Chen

Aaron Lee

Jing-Horng Gau

Pei-Jen Wang

Gow-Wei Sun

Steven Chen

Ga-Ming Hong

A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

Fabrication of self-aligned bipolar transistor

The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window. A second polysilicon layer is formed over the expitaxy base and the emitter window, wherein the second polysilicon layer has the second type ion. Finally, an etching process is introduced to etch the second polysilicon layer to form emitter plug. That is self-aligned to the emitter window.

Structure and method for forming self-aligned bipolar junction transistor with expitaxy base

A method for forming a STI structure. A pad oxide layer is formed over a substrate. A sacrificial layer is formed over the pad oxide layer. A mask layer is formed over the sacrificial layer. The mask layer is patterned, and then the sacrificial layer, the pad oxide layer and the substrate are etched in sequence to form a trench. A thermal oxidation is performed to form a liner layer along the exposed sidewalls of the sacrificial layer and the exposed substrate surface inside the trench. Insulation material is deposited over the substrate, completely filling the trench. A chemical-mechanical polishing step is performed to remove a portion of the insulation layer and a portion of the mask layer so that an insulation plug is formed inside the trench. After the polishing step, the top surface of the insulation plug and the top surface of the mask layer are at the same surface. The mask layer is patterned to expose a portion of the sacrificial layer near the central region of two neighboring trenches. An ion implantation is carried out. The mask layer and the sacrificial layer are removed.

Method for forming shallow trench isolation structure

A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses. A second measuring step is performed to measure a third thickness loss from the first etch stop layer exposed by the monitoring opening on the wafer. The result is then compared with the correlation to deduce a fourth thickness loss from the first contact opening on the wafer.

Method of monitoring loss of silicon nitride

An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region. The drain region is on one side of the terminal contact corresponding to the source region.

Method of fabricating dynamic random access memories

A method for forming a STI structure. A pad oxide layer is formed over a substrate. An amorphous silicon layer is formed over the pad oxide layer. A mask layer is formed over the amorphous silicon layer. The mask layer is patterned, and then the amorphous silicon layer, the pad oxide layer and the substrate are etched in sequence to form a trench. A thermal oxidation is performed to form a liner layer along the exposed sidewalls of the amorphous silicon layer and the exposed substrate surface inside the trench. Insulation material is deposited over the substrate, completely filling the trench. A chemical-mechanical polishing step is performed to remove a portion of the insulation layer and a portion of the mask layer so that an insulation plug is formed inside the trench. After the polishing step, the top surface of the insulation plug and the top surface of the mask layer are at the same surface. The mask layer is patterned to expose a portion of the amorphous silicon layer near the central region of two neighboring trenches. An ion implantation is carried out. The mask layer is removed. The amorphous silicon layer is removed.

Method for forming a shallow trench isolation structure

A fabrication method for a compact DRAM cell is described. The method includes forming a first doped polysilicon layer, a metal barrier layer, a second doped polysilicon layer, a metal silicide layer and a patterned silicon oxide layer on a semiconductor substrate. A first silicon nitride spacer is then formed on the sidewall of the patterned silicon oxide layer, followed by a removal of the patterned silicon oxide layer and parts of a metal silicide layer, the second doped polysilicon layer and the metal silicide layer to form an upper part of the gate. A second silicon nitride spacer is then formed on the sidewall of the upper part of the gate, followed by a removal of the exposed first doped polysilicon layer to form the lower part of the gate. A bit line contact and a node contact are subsequently formed on both side of the gate above the lower part of the gate.

Fabrication method for a compact DRAM cell

A method of fabricating dynamic random access memory. A conductive layer, a metal silicide layer, a first cap layer and a second cap layer are formed and patterned to form gate structures on the substrate. A first oxide layer is formed over the sidewalls of the metal silicide layer and the conductive layer as well as over the exposed substrate. First spacers are formed on the sidewalls of the gate structures. A second oxide layer is formed over the substrate. Second spacers are formed on the sidewalls of the second oxide layer. A third oxide layer is formed over the substrate. The second spacers, the second oxide layer and a portion of the first oxide layer are removed to expose a portion of the substrate. Contact pads that expose the second cap layer and a portion of the first spacers are formed, and then a first dielectric layer is formed over the entire substrate. Source/drain regions are formed on each side of the third oxide layer in the substrate. Bit lines that connect electrically with the contact pad through a contact in the first dielectric layer are formed. A second dielectric layer is formed over the entire substrate. A storage node electrode that connects electrically with the contact pad through a contact in the second dielectric layer is formed.

Method of manufacturing dynamic random access memory

A fully self-aligned method for fabricating a transistor is described. The source/drain contact opening is formed in the forming step of the gate to avoid the problem of misalignment. Therefore, the complex processes and the poly pad layer of the conventional method are not needed. A fully self-aligned method for fabricating memory is described. The memory cell and logic circuit regions have the same height during the formation process of the memory.

Fully self-aligned method for fabricating transistor and memory

A method for fabricating a capacitor in DRAM. A horizontal buried doped region is formed in a substrate. A pad oxide layer and a mask layer are formed in sequence on the substrate. A plurality of first trenches is formed in the substrate. Thus, a plurality of bit lines is formed in the substrate. A plurality of second trenches is formed in the substrate to expose the surface of the bit lines, wherein the second trenches cross the first trenches. Thus, a plurality of silicon islands on the bit lines is formed. A first insulation layer is formed in the first trenches and the second trenches, wherein the sidewall of the silicon islands are partly exposed and doped regions are formed in the exposed sidewall. A gate oxide layer is formed on the sidewall of the silicon islands. A spacer is formed on the gate oxide layer. A second insulation layer is formed over the substrate. The mask layer and the pad oxide layer are removed to expose the top surfaces of the silicon islands. A patterned conductive layer is formed over the substrate. A dielectric layer and an upper electrode are formed in sequence over the substrate.

Method for fabricating capacitor

A method of forming a dynamic random access memory cell such that the gate conductive layer, the bit line contact, the node contact, the bit line and the node contact plug are all formed using self-aligned processes. By employing the self-aligned method of forming DRAM cell, isolation structures are no longer etched in the process of forming the node contact opening. In addition, the aspect ratio of the node contact opening is reduced and processing window is thereby widened.

Method of forming self-aligned DRAM cell

A method for forming a STI structure is provided. The method contains sequenitially forming a pad oxide layer and a mask layer on a semiconductor substrate. Several trenches in the substrate through the mask layer and the pad oxide layer. The trenches has a wider trench and a narrower trench. A liner oxide layer is formed at each sidewall of the trenches in the substrate. A spacer is formed on each sidewall of the wider trench, in which the narrower trench simultaneously is filled with same insulating material. A conformal polysilicon layer is formed over the substrate, in which the wider trench is not completely filled yet. An insulating plug is formed to fill the wider trench. Using the insulating plug as an etching mask a portion of the polysilicon layer is removed by etching. As a result, a polysilicon pivot sidewall of the remaining polysilicon layer due to etching may occur. The polysilicon pivot sidewall is compensated with polysilicon. The mask layer and the pad oxide layer are removed, and a gate oxide layer is formed instead. During the formation of the gate oxide layer, a surface portion of the polysilicon layer is also oxidized so that the insulating plug and the spacer are merged through the oxidized portion of the polysilicon to form a round isolation structure.

Method for fabricating a shallow trench isolation structure

The invention is a method for fabricating a capacitor in a dynamic random access memory. The capacitor has double cylinder structure and is fabricated by utilizing an insulating side wall spacer to pre-define the capacitor structure. Then, a wet etching process is applied to remove the insulating side wall spacer and expose a surface of a structured lower electrode. Then, a dielectric thin film and an upper electrode are formed over the surface of the lower electrode sequentially to form the capacitor.

Method for fabricating a capacitor in a dynamic random access memory

A method of fabricating a dual cylindrical capacitor in a DRAM. A semiconductor substrate comprising a gate, a source/drain region, field oxide layer, a first oxide layer covering the whole semiconductor substrate, and a poly-via penetrating through the first oxide layer to electrically connect the source/drain region is provided. A first poly-silicon layer is formed on the first oxide layer and the poly-via. A silicon nitride layer is formed and patterned on the first poly-silicon layer and aligned with the poly-via. An oxide spacer is formed on a side wall of the silicon nitride layer, so that a part of the first poly-silicon layer is covered by the oxide spacer. A part of the first poly-silicon layer is removed with the oxide spacer and the silicon nitride layer as a mask until the first oxide layer is exposed. The silicon nitride layer is removed. A poly-silicon spacer is formed around the oxide spacer. The oxide spacer is removed, so that the remaining first poly-silicon layer and the poly-silicon spacer are combined as a bottom electrode. A dielectric layer is formed on a surface of the electrode. A top electrode is formed on the dielectric layer.

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Hsinchu Hsien, Taiwan

Shu-Ya Chuang