Yangtze Memory Technologies Co., Ltd.

Shu Wu

Liang Xiao

He Chen

Yong Qing Wang

Zi Qun Hua

Siping Hu

Ziqun Hua

Yongqing Wang

Lina Miao

Pengan Yin

Zhen Pan

Yi Zhao

Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Three-dimensional memory devices and fabricating methods thereof

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes preparing a stacked device having a first array device and a second array device, forming an opening on a back side of the second array device, and forming one or more contact pads in the opening. The first array device includes first front pads on a face side of the first array device and first back pads on a back side of the first array device. The second array device includes second front pads on a face side of the second array device and bonded with the first back pads. The one or more contact pads are disposed at a level proximate to the second front pads with respect to the first array device.

Contact pads of three-dimensional memory device and fabrication method thereof

In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

Wafer stress control using backside film deposition and laser anneal

A fabricating method of a semiconductor device is provided. A temporary semiconductor structure is provided. The temporary semiconductor structure includes a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer includes one or more first trace. Then, a recess is formed in the temporary semiconductor structure to form a first semiconductor structure and a first substrate. The recess penetrates through the first substrate and expose the one or more first trace. Thereafter, an input/output pad is formed in the recess and on the one or more first trace.

Fabricating method of semiconductor device with exposed input/output pad in recess

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a semiconductor structure and an input/output pad. The semiconductor structure includes a first substrate and a conductive layer, in which the first substrate has a first surface and a second surface opposite to each other, the conductive layer is disposed on the first surface of the first substrate, and the conductive layer includes one or more first trace. The first semiconductor structure has a recess penetrating the first substrate and exposing the one or more first trace, and the input/output pad is disposed on the one or more first trace and in the recess.

Semiconductor device with exposed input/output pad in recess

Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first die and a second die boned face-to-face. The first die includes first transistors formed on a face side of the first die in a semiconductor portion and at least a contact structure disposed in an insulating portion outside the semiconductor portion. The second die includes a substrate and second transistors formed on a face side of the second die. Further, the semiconductor device includes a first pad structure disposed on a back side of the first die and the first pad structure is conductively coupled with the contact structure. An end of the contact structure protrudes from the insulating portion into the first pad structure. Further, in some embodiments, the semiconductor device includes a connection structure disposed on the back side of the first die and conductively connected with the semiconductor portion.

Pad structures for semiconductor devices

The present disclosure provides a method of fabricating a semiconductor device. The method can include bonding a first die and a second die face to face, the first die including a substrate, transistors formed on a face side of the first die over a semiconductor layer with an insulating layer between the substrate and the semiconductor layer, and a first contact structure on the face side of the first die extending through the insulating layer. The method can also include exposing the first contact structure from the back side of the first die, forming, from the back side of the first die, a contact hole in the insulating layer to expose the semiconductor layer, and forming, on the back side of the first die, a first pad-out structure connected with the first contact structure and a second pad-out structure, on the contact hole, conductively connected with the semiconductor layer.

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Wuhan, China

Shu Wu