United Microelectronics Corp.

Shu-Wei Yeh

Chang-Hung Chen

Yu-Tse Kuo

Chun-Hsien Huang

Shu-Ru Wang

Chun-Yen Tseng

Yi-Ting Wu

Ya-Lan Chiou

Tsung-Hsun Wu

Chih-Ming Su

Zhi-Xian Chou

Wei-Chi Lee

Han-Tsun Wang

The invention provides a layout pattern cell of a static random access memory (SRAM), which at least comprises a first SRAM cell, a plurality of gate structures spanning a plurality of fin structures, so as to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor located on a substrate, the first parasitic transistor and the first pull-down transistor span the same fin structure, and the fin structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

Layout pattern for static random access memory

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Layout pattern of magnetoresistive random access memory

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU, a first pull-down transistor PD, a second pull-up transistor PU, a second pull-down transistor PD, a first pass gate transistor PG, a second pass gate transistor PG, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PGand the fin structure of the second read transistor RPG.

Layout pattern of static random access memory and the manufacturing method thereof

The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU) and a first pull-down transistor (PD), the second inverter includes a second pull-up transistor (PU) and a second pull-down transistor (PD). A dummy layer crossing the first a region and the second region, and between the PDin the first region and the PDin the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device and a second pass gate device disposed on a substrate. A plurality of fin structures are disposed on the substrate, and the fin structures include at least one first fin structure and at least one second fin structure. A J-shaped gate structure is disposed on the substrate, including a long part, a short part and a bridge part. At least one first extending contact structure crosses over the at least one first fin structure and the at least one second fin structure, wherein the at least one first extending contact structure does not overlap with the bridge part of the J-shaped gate structure.

A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.

Growing community of inventors

Taichung, Taiwan

Shu-Wei Yeh