Aspiring Sky Co. Limited

Basf Se Corporation

Shu Wang

Zhijiong Luo

Xiaoming Jin

Achim Loeffler

Christian Koenig

Dejan Petrovic

Daniel Freidank

Andreas Bauder

Isa Alexandra Queiroz Da Fonseca

Siqi Xue

Dirk Opfermann

Caroline Mages-Sauter

Ying Ying Dai

Chuan Long Fu

Zuqu Li

A memory system may include one or more hybrid fast memory blocks with m-bit fast volatile random access memory (RAM) cells and N&#xd7;m bit non-volatile memory (NVM) cells. The memory system may also include one or more other memory blocks with NVM cells. The fast flash memory may buffer the NVM data improving access speed. The different memory blocks may utilize a single, unified interface to communicate with other devices/circuits. The unified interface may be a parallel interface (e.g., flash memory/SRAM combinations), or the unified interface may be a pipeline interface (e.g., system on a chip 'SOC' implementations) supporting fast memory read/write operations.

Multi-block non-volatile memories with single unified interface

A polyamide composition with improved melt flow containing (A) 20 to 99.9 wt % of one or more polyamides independently selected from the group consisting of aliphatic polyamide, semi-aromatic polyamide, aromatic polyamide and their blends, (B) 0.1 to 10 wt % of one or more polyether polyols having a melting temperature below room temperature, (C) 0 to 70 wt % of one or more reinforcing agents, and (D) 0 to 50 wt % of one or more other additives, each based on the whole composition. A molding article produced from the polyamide composition also is disclosed.

Polyamide compositions with high melt flow and good mechanical properties

Technologies are generally described herein for a hybrid non-volatile memory structure that includes a number of SRAM buffers. SRAM access times may be achieved for non-volatile read/write operations by performing access queue buffered read/write operations first. The SRAM buffer may be shareable as a system SRAM. In other examples, a hybrid non-volatile memory according to some embodiments may include a high speed block and a high endurance block to store different types of data with different access needs. The hybrid non-volatile memory may also include a normal block to store the data which is non-frequently changed.

Hybrid non-volatile memory devices with static random access memory (SRAM) array and non-volatile memory (NVM) array

A memory system includes a code flash and data flash merged flash memory, which may contain a code flash with differential cell structure, a data flash with single cell structure, decoder circuitry, a sense amplifier, and other suitable support circuitry. The code flash and data flash may be located in a same plane or multi planes. In some examples, the code flash may be also accessed to read while the data flash is performing write operation, and vice versa.

Hybrid flash memory structure

Technologies are described for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.

Re-configurable non-volatile memory structures and systems

This invention relates to a continuous process for making a polymer polyol, the polymer polyol produced according to the said process and its applications.

Process for making a polymer polyol

Memory structures are provided, where a fast SRAM in an mNVSRAM block may serve as the buffer for a large block NVM memory to increase the data exchange rate between computing units or processor cores and the large NVM memory. The mNVSRAM blocks may also provide a fast boot function, where a boot code may be stored in the NVM parts of the mNVSRAM block, and due to the high bandwidth communication between fast SRAM part and the associated NVM memories, the boot code may be transferred into the fast SRAM in one or a few clock cycles enabling fast boot up function. Similarly, code stored in the NVM parts of an mNVSRAM block may be transferred into fast SRAM rapidly at wake-up time enabling fast wake up and voiding a need to wake up any other memory part, which may also result in energy savings for the computing system.

Low power non-volatile SRAM memory systems

Technologies are generally described herein for static random access memory (SRAM) based memory structures and methods thereof such as multi-bit non-volatile static random-access memory (nvSRAM) with arrayed SRAM and NVM or SRAM buffered one time programmable (OTP) memories, RRAMs or other resistive RAMs.

Growing community of inventors

Shanghai, China

Shu Wang