Renesas Technology Corp.

Renesas Electronics Corporation

International Business Machines Corporation

Mitsubishi Denki Kabushiki Kaisha

Other

Ryoden Semiconductor System Engineering Corporation

Shu Shimizu

Kojiro Yuzuriha

Takashi Yano

Tamotsu Tanaka

Hideaki Komatsu

Masana Murase

Ippei Shimizu

Gang Zhang

Kohichi Kajitani

A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.

Method of manufacturing semiconductor device

System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators.

Simulation method, system, and program

A technique for increasing the speed of parallel running of logical processes without sacrificing the accuracy of data update timing in a parallel discrete event simulation system. A logical process involving a longer receiving time lag than that of sending is executed by an amount of initial shift for a predetermined period before the simulation. The initial shift is set to be one-half of a value of difference between the receiving time lag and the sending time lag. The logical process executed with timing displaced by the amount of initial shift runs by exchanging null messages with each other. Each null message is delivered to a correspondent logical process after the predetermined time lag, and each logical process further sends the correspondent logical process a null message upon receipt of the null message. Thus, there is a progression of simulation by synchronizing them through the null messages.

Simulation execution method, program, and system

An isolation oxide film whose upper surface is higher than a surface of a substrate is formed in the substrate. A silicon oxide film is formed on the substrate between the isolation oxide films. A self-aligned polysilicon film is formed on the silicon oxide film between the isolation oxide films. After forming a resist pattern covering the peripheral circuitry, the isolation oxide films in the memory cell are etched by a predetermined thickness. An ONO film is formed on the entire surface of the substrate, a second resist pattern covering the memory cell is formed. Then, the ONO film, the polysilicon filmand the silicon oxide filmare removed from the peripheral circuitry.

Method for manufacturing non-volatile semiconductor memory device, and non-volatile semiconductor memory device

A semiconductor device ensuring an isolation of elements by a trench is provided. A method of manufacturing the semiconductor device includes the step of forming a silicon nitride film having an aperture, the step of selectively removing a part of a silicon substrate along aperture to form a recess defined by a side surface and a bottom surface in silicon substrate, the step of oxidizing the side surface and the bottom surface of the recess to form a thermal oxide film having a side portion and a bottom portion, and the step of selectively removing bottom portion of thermal oxide film and a part of silicon substrate by using silicon nitride film as a mask to form a trench.

Manufacturing method of semiconductor device

A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.

Method of manufacturing semiconductor device and flash memory

A nonvolatile semiconductor memory device that can be miniaturized is provided. A method of manufacturing the nonvolatile semiconductor memory device includes the steps of: forming an interlayer insulating film covering a stacked structure and a sidewall insulating film and having a top surface approximately parallel to a main surface; forming a resist pattern as a mask layer on the top surface of the interlayer insulating film; forming a groove as an opening in the interlayer insulating film to be positioned between the sidewall insulating films formed at the adjacent stacked structures; and forming a source region extending along a plurality of floating gate electrodes by implanting impurity ions from the groove to the main surface.

Nonvolatile semiconductor memory device and manufacturing method thereof

A nonvolatile semiconductor memory device including a semiconductor substrate , a plurality of memory cells on the semiconductor substrate including transistors having floating gate electrodes and control gate electrodes. Source lines are formed in a self-alignment manner with respect to a control gate electrodes. The surface of the semiconductor substrate has such a periodical unevenness along the source lines which has a diffusion layer that an impurity is distributed along the surface of the semiconductor substrate and a buried diffusion layer that an impurity is distributed at a position deeper than said diffusion layer . The buried diffusion layer connects a plurality of portions of the diffusion layers under the bottom surface of the recess portion to each other.

Nonvolatile semiconductor memory device

A semiconductor device is provided which is capable of reducing the number of masking processes in forming contact holes. The semiconductor device comprises a semiconductor substrate ( ), a gate structure ( ), a stopper film ( ), an interlayer insulation film ( ), a contact hole ( ) extending from the upper surface ( ) of the interlayer insulation film ( ) to the semiconductor substrate ( ), a metal material ( ) buried in the contact hole ( ), a first metal wiring layer ( ), an interlayer insulation film ( ), a contact hole ( ) extending from the upper surface ( ) of the interlayer insulation film ( ) to the first metal wiring layer ( ), and a contact hole ( ) extending from the upper surface ( ) of the interlayer insulation film ( ) to a gate electrode ( ) of the gate structure ( ). The contact hole ( ) is formed at the same time as the contact hole ( ).

Semiconductor device

Binary mode memory cells each storing data of a single bit per cell and multilevel mode memory cells each storing data of multi bits per cell are allocated with different address regions in a fixed manner and are formed in different regions. According to the fixed address allocation, the binary mode memory cells and the multilevel mode memory cells can be optimized individually and separately. In this way, the reliability of a nonvolatile semiconductor memory device is improved and the area occupied by the memory arrays is reduced.

A highly reliable semiconductor device capable of preventing generation of a leakage current is provided. The semiconductor device comprises a silicon substrate having a main surface and including a trench formed on the main surface. The trench is defined by surfaces including a bottom surface, a side surface, continuous to the bottom surface, having first inclination with respect to the main surface, and an intermediate surface, formed between the main surface and the bottom surface, having second inclination smaller than the first inclination with respect to the main surface. The semiconductor device further comprises an n-type impurity region.

Semiconductor device and method of fabricating the same

A non-volatile semiconductor memory device includes a plurality of trenches for element-isolation formed on the main surface of a semiconductor substrate, a nitrided silicon layer formed along the wall surface of the trench, a silicon oxide film for element-isolation formed in the trench, a thermal oxide film extending from the aforementioned main surface located at the periphery of the nitrided silicon layer onto the nitrided silicon layer, the thickness of a portion located on the nitrided silicon layer of which is not less than the thickness of a portion located at the periphery of nitrided silicon layer, a floating gate electrode formed on the thermal oxide film, an insulating film, and a control gate electrode.

Non-volatile semiconductor memory device and method of manufacturing the same

A nonvolatile semiconductor memory device includes a semiconductor substrate having a main surface, a floating gate electrode having a doped polycrystalline silicon film formed on the main surface with a thermal oxide film therebetween, and a doped polycrystalline silicon film laid over the doped polycrystalline silicon film and having an upward wall, an insulating film covering the doped polycrystalline silicon film, and a control gate electrode formed on the insulating film.

Growing community of inventors

Hyogo, Japan

Shu Shimizu