E Ink Holdings Inc.

Shu-Ping Yan

Chi-Ming Wu

Pei-Lin Huang

Ming-Sheng Chiang

Shu-Hao Chang

Chia-Chun Yeh

Ian French

Wei-Chou Lan

Chih-Cheng Wang

Ta-Nien Luan

Chun-Wei Hsieh

Yi-Lung Wen

Kai-Mao Huang

Yi-Ming Wu

Wei-Te Huang

Chin-Hsuan Kuan

A circuit protection structure applied to a gate driver that is in a display panel (GIP) is provided. The gate driver has a first metal layer, a first isolation layer, a semiconductor layer, a second metal layer, and a second isolation layer. The first metal layer, the first isolation layer, the semiconductor layer, the second metal layer, and the second isolation layer are stacked in sequence. The circuit protection structure includes a protection layer. The protection layer is located on the second isolation layer.

Circuit protection structure and display device having the same

A manufacturing method for a display module is provided. The method comprises following steps. A module structure comprising a cover plate, a substrate, and a front plate disposed between the cover plate and the substrate is provided. A space is defined by a lower surface of the cover plate, an upper surface of the substrate, and a side surface of the front plate. A holding structure comprising a holding layer disposed under the module structure is provided. A sealant is filled into the space. Portions of the package layer and the holding structure disposed outside a side surface of the cover plate and a side surface of the substrate are removed.

Manufacturing method for display module

A pixel array including first and second signal lines, an active device, a pixel electrode and selection lines is provided. The second signal lines are intersected with the first signal lines to drive the active device, and the pixel electrode is connected to the active device. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines, where at least one selective line is disposed between the adjacent two second signal lines. An amount ratio of the first signal lines and the selection lines is a/a, where a&#x2266;a, and when aand aare mutually prime numbers, the selection lines are divided into a plurality of groups, and each group includes aselection lines electrically connected to the first signal lines, and (a&#x2212;a) selection lines not electrically connected to the first signal lines.

Pixel array comprising selection lines

A pixel array includes multiple scan lines, multiple gate lines, multiple data lines and multiple pixel structures. The scan lines are disposed on a substrate. The gate lines intersect with the scan lines to demarcate multiple first unit regions and multiple second unit regions. Each gate line electrically connects to one of the scan lines. The data lines intersect with the scan lines and pass through the first unit regions. Each data line is located between two adjacent gate lines. The pixel structures are disposed on the first unit regions. Each pixel structure includes an active device and a pixel electrode. The active device is driven by one corresponding scan line and connects with one corresponding data line. An orthographic projection of each pixel electrode on the substrate is non-overlapped with or incompletely overlapped with an orthographic projection of the corresponding gate lines on the substrate.

Pixel array

A pixel array includes a plurality of first and second signal lines, a plurality of active devices, a plurality of pixel electrodes, a plurality of selection lines, and a plurality of protrusions. The second signal lines are electrically insulated to and intersected with the first signal lines. Each active device is electrically connected to one of the first signal lines and one of the second signal lines, respectively. The pixel electrodes are electrically connected to the active devices. The selection lines are electrically insulated to the second signal lines and intersected with the first signal lines so as to form a plurality of intersections including a plurality of first and second intersections. The selection lines are electrically connected to the first signal lines at the first intersections. The protrusions are disposed between the selection lines and the first signal lines, and located at the second intersections.

An active device array substrate includes a substrate, first signal lines, second signal lines, pixel units, selection units, an insulating layer, and a driving unit. The second signal lines and the selection lines are electrically connected with the driving unit. The insulating layer is disposed among the first signal lines, the second signal lines and the selection lines and has contact holes. The contact holes are disposed corresponding to the first signal lines, and a portion of the selection lines are electrically connected with the first signal lines via the contact holes. The selection line corresponding to the contact hole the farthest from the driving unit and the closest to a reference axis of the substrate and the selection line corresponding to the contact hole the closest to the driving unit and the reference axis respectively receive a start signal and a terminal signal provided by the driving unit.

Active device array substrate

A backlight display device includes a pixel region, a light-emitting region, a control element, a plurality of first flexible printed circuit board (FPCB) contacts, and a plurality of first driving circuits. The pixel region has a first edge, a second edge opposite to the first edge, a third edge, and a fourth edge opposite to the third edge. A corner region is formed between the first edge and the fourth edge. The light-emitting region is located on the corner region of the pixel region. The control element is located on the corner region of the pixel region and between the light-emitting region and the first edge. The first FPCB contacts are located on the second edge. Each of the first driving circuits is electrically connected to one of the first FPCB contacts and the control element.

Backlight display device

A test structure of a display panel is provided. The display panel has a display region, a non-display region, and a buffer display region between the display region and non-display region. The test structure is within the buffer display region and includes a substrate, at least one signal line on the substrate, an insulation layer covering the signal line, a planar layer on the insulation layer, and an electrode layer on the planar layer. The planar layer has at least one opening exposing a portion of the insulation layer. The electrode layer has a display electrode portion on the planar layer, at least one test electrode portion connecting the insulation layer via the opening of the planar layer, and a ring-like opening that surrounds the test electrode portion and exposes a portion of the planar layer. The display electrode portion surrounds the ring-like opening and connects the test electrode portion.

Test structure of display panel and testing method thereof and test structure of tested display panel

A bonding structure includes a substrate, multiple first pads, multiple second pads, an insulation layer and a patterned conductive layer. The substrate has a bonding region and a predetermined-to-be-cut region. The first pads are disposed on the substrate and within the bonding region. The second pads are disposed on the substrate and within the predetermined-to-be-cut region. The insulation layer is disposed on the substrate and covers the first and second pads. The insulation layer has multiple first and second openings respectively exposing parts of the first and second pads. The patterned conductive layer is disposed on the substrate and covers the insulation layer and the parts of the first and second pads exposed out by the first and second openings, in which the patterned conductive layer is electrically connected to the first and second pads via the first and second openings.

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Hsinchu, Taiwan

Shu-Ping Yan