Winbond Electronics Corporation

Shu-Ming Li

Tzu-Ming Ou Yang

Keng-Ping Lin

Chung-Ming Yang

Tetsuharu Kurokawa

Po-Yen Hsu

Yung-Han Chiu

Chia-Hung Liu

Ko-Po Tseng

A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Manufacturing method of memory structure

A manufacturing method for a memory structure including the following steps is provided. A bit line structure is formed on the substrate. A contact structure is formed on the substrate on one side of the bit line structure. A capacitor structure is formed on the contact structure. The capacitor structure includes a first electrode, a second electrode and an insulating layer. The first electrode is disposed on the contact structure in a misaligned manner. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is disposed on the contact structure. The second electrode is located on the first electrode. The insulating layer is disposed between the first electrode and the second electrode.

Manufacturing method for memory structure

Provided is a memory device including a substrate, a plurality of landing pads, a protective layer, a filling layer, a plurality of cup-shaped lower electrodes, a capacitor dielectric layer, and an upper electrode. The landing pads are disposed on the substrate. The protective layer conformally covers sidewalls of the landing pads. The filling layer is laterally disposed between the landing pads, wherein the filling layer has a top surface higher than a top surface of the landing pads. The cup-shaped lower electrodes are respectively disposed on the landing pads. The capacitor dielectric layer covers a surface of the cup-shaped lower electrodes. The upper electrode covers a surface of the capacitor dielectric layer. A method of forming a memory device is also provided.

Memory device and method of forming the same

A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.

Method of forming the semiconductor device

A method for manufacturing a semiconductor device includes forming contacts disposed in a dielectric layer. The method of forming the contacts includes forming contact holes and then filling with a conductive material. The method of forming the contact holes includes steps of forming openings in the dielectric layer to expose active regions, introducing a first oxygen plasma and a first fluorine plasma to remove by-products and oxidize inner surfaces of the openings, introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surfaces and repair the active regions, introducing a third oxygen plasma to oxidize inner surfaces again to form an oxide layer, and removing the oxide layer. The cross-sectional structure of two adjacent contact holes includes a capital, a base, and a shaft between the capital and the base, wherein the shaft has a smaller width than the base and the capital.

Method for manufacturing semiconductor device

Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Landing pad structure

A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

Memory structure and manufacturing method thereof

A semiconductor device and method of forming the same are provided. The semiconductor device includes a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is laterally aside the memory structure and covers sidewalls of the memory structure. A first dielectric layer is on the spacer layer and laterally aside the memory structure. A second dielectric layer is on the memory structure, the spacer layer and the first dielectric layer. A second conductive line penetrates through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple to the memory structure. The second conductive line includes a body part at least partially embedded in the second dielectric layer and an extension part underlying the body part and laterally protruding from a sidewall of the body part. The extension part is electrically connected to an upper electrode of the memory structure and surrounded by the spacer layer.

Semiconductor device and method of forming the same

A memory structure including a substrate, a bit line structure, a contact structure, and a capacitor structure is provided. The bit line structure is located on the substrate. The contact structure is located on the substrate on one side of the bit line structure. The capacitor structure is located on the contact structure. The capacitor structure includes a first electrode, a second electrode, and an insulating layer. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is only located on a part of the contact structure. The second electrode is located on the first electrode. The insulating layer is located between the first electrode and the second electrode.

Memory structure and manufacturing method therefor

A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate having a plurality of active regions, at least one dielectric layer formed on the substrate, and a plurality of contacts disposed in the dielectric layer and contacting with the active regions. The contact is a barrel-shaped structure with a middle portion, a head portion having a perimeter small than that of the middle portion, and an end portion having a perimeter small than that of the middle portion.

Semiconductor device and manufacturing method of the same

Landing pad structure and method of manufacturing the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a plurality of gate structures, a plurality of dielectric structures, and spacers. The plurality of gate structures is disposed on the substrate. The plurality of dielectric structures is respectively disposed between the gate structures and the substrate, wherein a top width of the dielectric structure is less than the bottom width of the dielectric structure. The spacers are disposed on the sidewalls of the gate structures and cover the sidewalls of the dielectric structures.

Semiconductor structure and manufacturing method thereof

A semiconductor device is provided. The semiconductor device includes a core structure, a first pattern and a second pattern. The core structure is disposed on a substrate. The first pattern covers a sidewall of a bottom portion of the core structure. The top surface of the first pattern is lower than a top surface of the core structure. The second pattern is disposed on the first pattern and covering a top portion of the core structure. A sidewall of the top portion of the core structure and the top surface of the core structure are covered by the second pattern. The second pattern has an upper portion tapered away from the substrate. A material of the first pattern is different from a material of the second pattern.

Semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. A core structure and a first material layer are formed on a substrate in order. A top surface of the first material layer is lower than a top surface of the core structure. A second pattern is formed on an exposed surface of the core structure. The method of forming the second pattern includes forming a second material layer on the exposed surface of the core structure and the top surface of the first material layer and performing an anisotropic etching on the second material layer. The first material layer is patterned by using the second pattern as a mask to form a first pattern. The step of forming the second material layer and the step of performing an anisotropic etching on the second material layer are performed in the same etching chamber.

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Taichung, Taiwan

Shu-Ming Li