Winbond Electronics Corporation

Shu-Ming Lee

Tzu-Ming Ou Yang

Yung-Han Chiu

Meng-Chang Chan

Chia-Hung Liu

Chun-Chieh Wang

Po-Han Wu

Ling-Chun Tseng

Pai-Chun Tsai

A semiconductor structure and its manufacturing method are provided. A semiconductor structure includes a substrate and several bit lines on the substrate. Each of the bit lines includes a first conductive layer on the substrate, a second conductive layer on the first conductive layer, and a hardmask layer on the second conductive layer. The semiconductor structure further includes several contacts disposed on the substrate and positioned between two adjacent bit lines, wherein the bottom surfaces of the contacts physically contact the substrate. The top surfaces of the contacts are not higher than the top surfaces of the hardmask layers. Each of the contacts includes a bottom contact part on the substrate and a top contact part on the bottom contact part, and a width of a top surface of the top contact part is greater than a width of a top surface of the bottom contact part.

Semiconductor structure and method of manufacturing the same

A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Method for forming a semiconductor structure

A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Method of manufacturing semiconductor structure

Semiconductor structure and method for forming the same

A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Memory device

A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.

Memory devices and methods for forming the same

Memory device and method for manufacturing the same

A memory device and a method for manufacturing the memory device are provided. The memory device includes two first gate structures and a multilayer insulating structure. The multilayer insulating structure includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer sequentially from bottom to top. The width of the second insulating layer is equal to that of the third insulating layer, and smaller than that of the first insulating layer. The width of the bottom surface of the fourth insulating layer is greater than the width of the top surface of the third insulating layer. The memory device includes a capacitor contact plug formed between the first gate structures. The capacitor contact plug includes a first contact element, a buffering layer, and a second contact element. The second contact element has a top surface wider than its bottom surface.

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Taichung, Taiwan

Shu-Ming Lee