Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu-Min Chen

Li-Chun Tien

Pin-Dai Sue

Yung-Chin Hou

Ru-Gun Liu

Lee-Chung Lu

Ta-Pen Guo

Tsong-Hua Ou

Shyue-Shyh Lin

Chung-Cheng Wu

Jung-Chan Yang

Min Cao

Hsiang-Jen Tseng

Chun-Hui Tai

Ali Keshavarzi

Ann Luh

Ping Chung Li

Andy Hong

Oliver Wu

Helen Shu-Hui Chang

Kathy Wang

A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of FinFETs; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer.

Adaptive fin design for FinFETs

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Integrated circuits and manufacturing methods thereof

A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.

Integrated circuit layouts with power rails under bottom metal layer

An integrated circuit structure includes a semiconductor substrate; a first active region in the semiconductor substrate; and a second active region in the semiconductor substrate and of an opposite conductivity type than the first active region. A gate electrode strip is over the first and the second active regions and forms a first MOS device and a second MOS device with the first active region and the second active region, respectively. A first spacer bar is in the semiconductor substrate and connected to the first active region. At least a portion of the first spacer bar is adjacent to and spaced apart from a portion of the first active region. A second spacer bar is in the semiconductor substrate and connected to the second active region. At least a portion of the second spacer bar is adjacent to and spaced apart from a portion of the second active region.

Standard cell without OD space effect in Y-direction

A computer integrated manufacturing system executes a program process that performs a capacity planning method that allocates usage of a plurality of manufacturing elements of a manufacturing enterprise by major and minor apparatus, squeezing for overhead cost consideration, and site balance for maintain basic operation. The program process begins by receiving at least one fabrication forecast describing scheduling and types of product lots that are predicted to be fabricated within a first period of time by the manufacturing enterprise from at least one order management system of the manufacturing enterprise. Rolling statistics of products lots fabricated during a second period of time are retrieved from a data retention device of the computer integrated manufacturing system. Capacity planning for the allocation of the product lot predicted to be fabricated by the manufacturing elements is performed.

Heuristics for efficient supply chain planning in a heterogeneous production line

Growing community of inventors

Yongkang, Taiwan

Shu-Min Chen