Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Shu Kuan

Shahaji B More

Cheng-Han Lee

Shih-Chieh Chang

Huai-Tei Yang

Chien Lin

Zheng-Yang Pan

Chien-Feng Lin

Shih-Wei Hung

Shiming Lin

Long-Sun Huang

Kuang-Chong Wu

Yi-Kuang Yen

Yu-Fu Ku

Ping-Yen Lin

A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

Method of forming fully strained channels

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.

Method of manufacturing a semiconductor device and a semiconductor device

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.

In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

P-type strained channel in a fin field effect transistor (FinFET) device

A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison.

Method for detecting presence and location of defects in a substrate

A system for compensating a thermal effect is provided and includes a substrate structure and a microcantilever. The substrate structure includes a first piezoresistor. The first piezoresistor is buried in the substrate structure and has a first piezoresistance having a first relation to a first variable temperature. The microcantilever has the thermal effect and a second piezoresistance having a second relation to the first variable temperature, wherein the thermal effect is compensated based on the first and the second relations.

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Keelung, Taiwan

Shu Kuan