Elite Semiconductor Memory Technology, Inc

Shu-Han Nien

Jian-Sing Liou

An exemplary embodiment of the present disclosure illustrates a duty cycle correction apparatus for fast adjusting internal clocks to have specific duty cycles. Firstly, a reference clock is adjusted to have one specific duty cycle in response to analog feedback clocks. Then, by using a phase detector, phases of the reference clock and one internal clock are compared to generate a phase detection signal. Next, by using a digital-analog converter, complementary signals are generated according to a phase detection signal received by the counter, and the signals are used to adjust the duty cycles of the internal clocks. When the complementary signals make the duty cycle of the internal clock equals to the specific duty cycle, codes of the complementary signals are recorded.

Duty cycle correction apparatus

A bandgap reference circuit incorporates first, second, and third current sources, an operational amplifier coupled to the second and the third current sources, a voltage divider, a first resistor, and first, second, and third bipolar transistors. The second bipolar transistor has a base configured to receive a first voltage from the voltage divider. The third bipolar transistor has a base configured to receive a second voltage from the voltage divider. The first resistor is coupled between the third current source and the third bipolar transistor.

Bandgap reference circuit

A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.

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Changhua County, Taiwan

Shu-Han Nien