Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu Fang Fu

Chia-Chung Chen

Chi-Feng Huang

Victor Chiang Liang

Chewn-Pu Jou

Tzu-Jin Yeh

Fu-Huan Tsai

Chang-Sheng Liao

Tse-Hua Lu

Chung-Hao Chu

Yu-Lin Wei

Tsun-Lai Hsu

Fredrik Ramberg

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

Method of making a semiconductor device

Method of making a semiconductor device, semiconductor device and ring oscillator

The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.

Semiconductor structure and method of fabricating the semiconductor structure

A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.

RF switch on high resistive substrate

A method includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method includes forming a first source/drain feature between the gate structure and the first edge structure; and a second source/drain feature between the gate structure and the second edge structure. A distance between the gate structure and the first source/drain feature is from about 1.5 to about 4.5 times greater than a distance between the gate structure and the second source/drain feature. The method includes implanting a buried channel in the semiconductor strip. A top surface of the buried channel is spaced from a top surface of the semiconductor strip. A bottom surface of the buried channel is closer to the top surface of the semiconductor strip than a bottom surface of the first source/drain feature. A dopant concentration of the buried channel is highest under the gate structure.

Method of making a high speed semiconductor device

A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin. A distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature.

High speed semiconductor device

A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

High voltage metal-oxide-metal (HV-MOM) device, HV-MOM layout and method of making the HV-MOM device

A high voltage metal-oxide-metal (HV-MOM) device includes a substrate, a deep well in the substrate and at least one high voltage well in the substrate over the deep well. The HV-MOM device further includes a dielectric layer over each high voltage well of the at least one high voltage well and a gate structure over the dielectric layer. The HV-MOM device further includes an inter-layer dielectric (ILD) layer over the substrate, the ILD layer surrounding the gate structure. The HV-MOM device further includes a first inter-metal dielectric (IMD) layer over the ILD layer and a first metal feature in the first IMD layer, wherein the first metal feature is part of a MOM capacitor.

Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor.

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Xinpu, Taiwan

Shu Fang Fu