Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu-Chun Yang

Wen-Hung Huang

Mu-Shan Lin

Wei Chih Chen

Jinn-Yeh Chien

Yu-Nan Shih

An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Decision feedback equalization embedded in slicer

A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage. The first tunable capacitive element and the second tunable capacitive element are configured to be selectively turned on and off to provide different frequency responses.

Circuits, equalizers and related methods

A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage.

A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 &#x3bc;m. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.

Vertical noise reduction in 3D stacked semiconductor devices

Decision feedback equalization embedded in a slicer

An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.

Read-write data translation technique of asynchronous clock domains

A amplifier circuit in some embodiment includes a differential amplifier have a pair of current sources. Each of the current sources includes two or more current-generating transistors and respective switching transistors, which can be turned on and off by a gain input code to tune the gain of the amplifier. A common-mode controller includes a similar pair of current sources as the differential amplifier. The common mode controller receives a common-mode signal of the input signal and a common-mode gain input code, and maintains the common-mode gain of the amplifier circuit when the differential gain changes. The amplifier circuit is switchable between a buffer mode and an equalizer mode.

Tunable gain amplifier

A system and method is disclosed for adjusting for timing variations between a data signal and an associated data read signal being transmitted from a first chip and received on a second chip.

System and method for chip system timing compensation

This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.

Smart edge detector

In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D) to trigger a first flip-flop having a first clock in a transmitter domain (e.g., clock CLK_D) as input data for the first flip-flop. The clock CLK_Dthrough a delay cell also triggers a second flip-flop having the same clock CLK_Das input data for the second flip-flop. Based on the output of the first flip-flop (e.g., output S) and of the second flip-flop (e.g., output S), the embodiments determine whether the rising and or falling edge of clock CLK_Dshould be used for triggering in a transmitting and receiving application. The embodiments are applicable in both situations where the rising edge or falling edge of clock CLK_Dis used as a triggering edge. Other embodiments are also disclosed.

Growing community of inventors

Xihu, Taiwan

Shu-Chun Yang