Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

Shu-Chuan Lee

Ming-Hsiang Song

Yu-Der Chih

Jam-Wem Lee

Shao-Yu Chou

Yu-Ti Su

Jen-Chou Tseng

Chen-Ming Hung

Kuo-Ji Chen

Wade Ma

Jian-Hsing Lee

Kuo-Feng Yu

Ta-Lee Yu

Shi-Tron Lin

Shao-Chang Huang

Wei-Fan Chen

Yi-Hsun Wu

Tong-Chern Ong

Yu-Chen Lin

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Memory device with a fuse protection circuit

A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

An electrostatic discharge (ESD) protection circuit includes a field oxide device in a substrate, wherein the field oxide device is coupled between an input/output (I/O) pad and a first terminal. The field oxide device includes a drain end and a source end having a first type of dopant. The field oxide device includes a field oxide structure between the drain end and the source end. The field oxide structure has a top surface co-planar with a top surface of a substrate. A first doped region having a second type of dopant is adjacent to the drain end. A second doped region having the second type of dopant is adjacent to the source end. The field oxide structure is in a well and the source end and the drain end are separate from the well. The substrate has the second type of dopant and is around the field oxide structure.

Electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and methods for forming the ESD protection circuits

An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad is provided. The ESD protection circuit includes a first field oxide device coupled between a first terminal that is capable of providing a first supply voltage and the I/O pad. The first field oxide device includes a drain end having a first type of dopant and a source end having the first type of dopant. The first field oxide device includes a first doped region having a second type of dopant disposed adjacent to the drain end of the first field oxide device and a second doped region having the second type of dopant disposed adjacent to the source end of the first field oxide device.

Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

Electrostatic discharge protection device having light doped regions

A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.

High-voltage tolerance input buffer and ESD protection circuit

An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type is provided to includes a plurality of island-like distributed diffusion regions. The protection structure includes a semiconductor controlled rectifier (SCR), an MOS transistor and a plurality of island-like distributed diffusion regions of the first type. The semiconductor controlled rectifier is constructed on the base region and coupled to the integrated circuit. The SCR includes a first region of a second type formed next to the base region, a second region of the first type formed in the first region, and a third region of the second type formed in the base region. The MOS transistor has a drain coupled to the bonding pad or a VDD bus, and a gate and a source both coupled to a reference ground. The plurality of island-like distributed diffusion regions of the first type are formed in the base region and each is coupled to the reference ground.

ESD protection device with island-like distributed p&plus; diffusion regions

The present invention discloses an ESD damage immunity buffer, comprising: a gate, a first doped region, a second doped region, a third doped region, and a resist layer. The ESD damage immunity buffer, which is in parallel with an ESD protection circuit, is connected to a pad and the circuit grounding node. The gate is formed on the semiconductor substrate, and the first doped region and the second doped region are formed adjacent to the region below the gate in the semiconductor substrate and electrically coupled to the ground. The third doped region is formed in the semiconductor substrate and electrically coupled to the pad. Further, a resist layer is formed upon the semiconductor substrate and connects the third doped region to the second doped region, wherein said resist layer ensures a triggering of the ESD protection circuit prior to the ESD damage immunity buffer during an ESD event.

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Hsinchu, Taiwan

Shu-Chuan Lee