Arm Limited

Shruti Aggarwal

Ankur Goel

Mohit Chanana

Yew Keong Chong

Andy Wangkun Chen

Mudit Bhargava

Akshay Kumar

Rahul Mathur

Bikas Maiti

Piyush Agarwal

Hsin-Yu Chen

Munish Kumar

Kyung Woo Kim

Nitin Jindal

According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.

Methods and apparatuses of configurable integrated circuits

Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

Read assist circuitry for memory applications

To sense an impedance state of one or more correlated electron switch elements, a bit-line may be precharged to a voltage level that is less than a precharge voltage level for a sense amplifier, and a bit-line may be discharged through one or more correlated electron switch elements. A bit-line may be buffered from a sense amplifier via an electronic switch device.

Bit-line sensing for correlated electron switch elements

Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.

Write assist circuitry

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Noida, India

Shruti Aggarwal