Meta Platforms Technologies, LLC

Facebook Technologies, LLC

Shrirang Madhav Yardi

Alok Kumar Mathur

Bardia Zandian

Dinesh D Patil

Neeraj Upasani

Eugene Gorbatov

Pankaj Raghuvanshi

Vlad Fruchter

Gregory Ehmann

Javid Jaffari

Ennio Salemi

Nishant Sitapara

George Spatz

Jeffrey Ryden

A method by a computing system associated with a set of disjoint devices that includes at least one wearable device includes receiving a request to perform a task. The method further includes determining, based on sensor data associated with the set of disjoint devices, a thermal-constraint differential for each device of the set of disjoint devices. The method further includes determining a plurality of workload assignments needed to be performed to accomplish the task. The method further includes distributing, based on the thermal-constraint differentials of the set of disjoint devices, the plurality of workload assignments to one or more devices of the set of disjoint devices to satisfy one or more power or thermal constraints associated with each device of the set of disjoint devices. The method further includes performing the task by causing the one or more devices to execute the distributed plurality of work assignments.

Thermal management for extended reality ecosystem

Systems and methods for peak power control include control circuitry which identifies a condition for a device. The control circuitry can apply the condition for the device to one or more models maintained for a plurality of device processing units of the device to determine one or more performance characteristics for the plurality of processing units. The control circuitry can distribute power credits to the plurality of device processing units of the device according to the determined performance characteristics for the plurality of device processing units, to manage a respective peak power for each respective device processing unit according to a number of the power credits distributed to the respective device processing unit.

Systems and methods for peak power control

The disclosure describes artificial reality (AR) systems and techniques that enable hierarchical power management of multiple devices within a multi-device AR system. For example, a multi-device AR system includes a device comprising one of a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content. The device comprises a System on a Chip (SoC) that includes a host subsystem and plurality of subsystems. Each subsystem includes a child energy processing unit configured to manage power states for the subsystem. The host subsystem includes a parent energy processing unit configured to direct power management of each of the child energy processing units of the plurality of subsystems.

Hierarchical power management in artificial reality systems

The disclosure describes techniques for hierarchical power management of memory of an artificial reality system to reduce power consumption by the memory. An example device may be a peripheral device configured to generate artificial reality content for display or a head-mounted display unit (HMD) configured to output artificial reality content for display. The device includes memory divided into multiple memory blocks configurable to operate in a plurality of power modes. The device also includes memory block controllers controlling memory blocks. Each memory block controller controls which power mode in which the corresponding memory block is to operate, independent of any of the other memory blocks. The device includes a memory power controller configured to configure control registers of the memory block controllers to direct the memory block controllers to select one of the plurality of power modes for the memory blocks when the memory blocks are not being accessed.

Hierarchical power management of memory for artificial reality systems

A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.

Distributed phased SRAM repair for systems on a chip

Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.

Growing community of inventors

San Jose, CA, United States of America

Shrirang Madhav Yardi