Sandisk Technologies Inc.

Sandisk Corporation

Western Digital Technologies, Inc.

Advanced Micro Devices Corporation

Sandisk Semiconductor (shanghai) Co. Ltd.

Shrikar Bhagath

Hem P Takiar

Warren Middlekauff

Robert C Miller

Chin-Tien Chiu

Chih-Chin Liao

Ning Ye

Cheemen Yu

Michael K Patterson

Nagesh K Vodrahalli

Bo Yang

Rama Shukla

Pradeep Rai

Daniel Joseph Linnen

Kirubakaran Periyannan

Xu Wang

Jagdish Sabde

Ken Jian Ming Wang

Han-Shiao Chen

Chee Keong Chin

Junrong Yan

Eric Tosaya

Jack Chang Chien

Ashish Ghai

Alexander C Tain

Yangming Liu

Thomas S Tarter

Avinash Rajagiri

Srikar Peesari

Chun Sean Lau

Shantanu Gupta

Nhon T Do

Michael W Patterson

Kim Lee Bock

Tom Ley

Sukhminder Singh Lobana

Kaiyou Qian

Chong Un Tan

Ming Wu

Saurabh Nilkanth Athavale

Yuang Zhang

Lu Zhong

Hedan Zhang

Dean M Jenkins

Siqi Zhang

Srinivasan Sivaram

Chih Yang Li

Sean Lau

Bret Winkler

A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.

Power reallocation for memory device

A data storage device includes an enclosure and a Printed Circuit Board Assembly (PCBA) extending in a basal plane, and a plurality of semiconductor memory packages electromechanically bonded to the PCBA and coupled to the enclosure with thermal interface material. The data storage device further includes a first fitting coupled to a first end of the PCBA and the enclosure, restricting movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane. The data storage device further includes a second fitting coupled to a second end of the PCBA, allowing movement of the PCBA in the basal plane with respect to the enclosure and restricting movement of the PCBA out of the basal plane.

Enclosure fitting for electronic device

A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The substrate includes a top layer and a bottom layer. The first stack of memory dies is electrically coupled to the top layer of the substrate and includes a controller and a first number of memory dies. The second stack of memory dies is electrically coupled to the top layer of the substrate and includes a second number of memory dies greater than the first number of memory dies. An upper surface of the first stack of memory dies and an upper surface of the second stack of memory dies are substantially coplanar.

Semiconductor device with unbalanced die stackup

A method is disclosed herein. The method includes dicing a wafer and applying a mask. The method includes spraying die bond material, at a first temperature, to a surface of the wafer and cooling the die bond material at a second temperature to at least partially solidify the die bond material. The method also includes removing the mask from the wafer through the die bond material. After the removing of the mask, the method includes curing the die bond material to form a die attach film layer on the wafer.

Package process, DAF replacement

A packaged semiconductor device includes a substrate, a heat-generating component positioned on a surface of the substrate, an enclosure at least partially surrounding the substrate and the heat-generating component, and a thermal interface material disposed between the heat-generating component and the enclosure. The enclosure includes a cover portion having a convexly curved surface configured to apply a pressure to the thermal interface material. The pressure may be substantially uniform over the area of the thermal interface material, or may be higher at a center of the thermal interface material than at a periphery of the thermal interface material.

Semiconductor device package having cover portion with curved surface profile

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies.

Memory scaling semiconductor device

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. The semiconductor device may further include a CMOS logic circuit as part of the pair of semiconductor dies or in its own semiconductor die mounted to the pair of semiconductor dies.

A partial memory die is missing one or more components. One example of a partial memory die includes an incomplete memory structure such that the partial memory die is configured to successfully perform programming, erasing and reading of the incomplete memory structure.

Partial memory die

A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.

Semiconductor device including die bond pads at a die edge

A semiconductor wafer, die and semiconductor package formed therefrom are disclosed, where the inactive surface of the wafer has an extrinsic gettering pattern formed from a texturing process. In examples, the texturing process follows a polishing process that removes stress concentration point from the inactive surface of the wafer.

Extrinsic gettering on semiconductor devices

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

System-in-a-package based flash memory card

A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

Semiconductor device having under-filled die in a die stack

A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

Method of fabricating stacked semiconductor package with localized cavities for wire bonding

A low profile semiconductor package is disclosed including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with a plurality of redistribution pads formed over and electrically coupled to a plurality of bond pads. After the semiconductor die are formed and diced from the wafer, the die may be mounted to the substrate using a low profile reverse wire bond according to the present invention. In particular, a wedge bond may be formed between the wire and the redistribution pad without having to use a second wire bond ball on the die bond pad as in conventional reverse ball bonding processes.

Stacked wire bonded semiconductor package with low profile bond line

Growing community of inventors

San Jose, CA, United States of America

Shrikar Bhagath