Intel Corporation

Shrikant M Shah

Ren Wang

Stephen T Palermo

David Sonnier

William G Burroughs

Abhishek Khade

Gage Eads

Abhirupa Layek

Sarita Maini

Bradley Chaddick

Robert G Blankenship

Raanan Sade

Andrew J Herdrich

Christopher B Wilkerson

Anil Vasudevan

Vedaraman Geetha

Rahul R Shah

Niall D McDonnell

Chyi-Chang Miao

Binh Q Pham

Venkata Krishnan

Mrittika Ganguli

Marshall A Millier

Olivier Serres

Tsung-Yuan Charles Tai

Christian Maciocco

Ben-Zion Friedman

Hang T Nguyen

Sameh Gobriel

Sanjeev Jain

Srihari Makineni

Peter Munguia

Namakkal N Venkatesan

Peter Brink

Michael A O'Hanlon

Chetan J Rawal

Francesc Guim Bernat

Karthik Kumar

Thomas Willhalm

John Joseph Browne

Ankush Varma

Chris MacNamara

Vasudevan Srinivasan

Lokpraveen B Mosur

Edwin Verplanke

Rahul C Shah

Tomasz Kantecki

Nikhil Gupta

Dorit Shapira

Neelam Chandwani

Bruce Richardson

Chetan Hiremath

Patrick Lu

Rajesh Gadiyar

David Hunt

Uzair Qureshi

Pinkesh J Shah

Scott M Oehrlein

Shubha Bommalingaiahnapallya

John Mangan

Niall Mcdonnell

Praveen Mosur

Anatoly Burakov

Bryan T Butters

Rany ElSayed

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Systems, methods, and apparatus for workload optimized central processing units (CPUS)

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

Method and system for performing data movement operations with read snapshot and in place write update

Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

Platform slicing of central processing unit (CPU) resources

Devices and systems having memory-side adaptive prefetch decision-making, including associated methods, are disclosed and described. Adaptive information can be provided to memory-side controller and prefetch components that allow such memory-side components to prefetch data in a manner that is adaptive with respect to a particular read memory request or to a thread performing read memory requests.

Application and processor guided memory prefetching

Technologies for dynamically managing data bus bandwidth usage of virtual machines include a network device that includes a data bus, one or more processors coupled to the data bus, and one or more throttled devices coupled to the data bus. Each throttled device is configured to use no more than an amount of bus bandwidth associated with at least one throttle value assigned to the corresponding throttled device. The network device is to assign functions to virtual machines, determine throttle values for each of the throttled devices utilized by the virtual machines to perform their assigned functions, and perform the assigned functions subject to the determined throttle values. Other embodiments are described and claimed.

Technologies for dynamically managing data bus bandwidth usage of virtual machines in a network device

Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.

Technologies for network packet cache management

Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.

Extended message signal interrupt

A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed.

Apparatus and method for high performance volatile disk drive memory access using an integrated DMA engine

Growing community of inventors

Chandler, AZ, United States of America

Shrikant M Shah