Lam Research Corporation

Shrikant Lohokare

Andrew D Bailey, Iii

Yunsang Kim

Arthur M Howald

David J Hemker

Joel M Cook

John Martin De Larios

Andras Kuthi

Mark Henry Wilcoxson

Seokmin Yun

Simon McClatchie

Stephan Hoffmann

Seong Hwan Cho

An apparatus, system and method for removing a damaged material from a low-k dielectric film layer include identifying a control chemistry, the control chemistry configured to selectively remove the damaged material from the low-k dielectric film layer, the damaged material being in a region where a feature was formed through the low-k dielectric film layer; establishing a plurality of process parameters characterizing aspects of the damaged material to be removed and applying the control chemistry to the low-k dielectric film layer, the application of the control chemistry being defined based on the established process parameters of the damaged material, such that the damaged material is substantially removed from the areas around the feature and the areas around the feature are substantially defined by low-k characteristics of the low-k dielectric film layer.

Method of damaged low-k dielectric film layer removal

A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.

System, method and apparatus for self-cleaning dry etch

A system and method for forming a planar dielectric layer includes identifying a non-planarity in the dielectric layer, forming one or more additional dielectric layers over the dielectric layer and planarizing at least one of the additional dielectric layers wherein the one or more additional dielectric layers include at least one of a spin-on-glass layer and at least one of a low-k dielectric material layer and wherein each one of the one or more additional dielectric layers having a thickness of less than about 1000 angstroms and wherein the one or more additional dielectric layers has a total thickness of between about 1000 and about 4000 angstroms.

Method for stress free conductor removal

In a plasma processing system, a method of reducing byproduct deposits on a set of plasma chamber surfaces of a plasma processing chamber is disclosed. The method includes providing a deposition barrier in the plasma processing chamber, the deposition barrier is configured to be disposed in a plasma generating region of the plasma processing chamber, thereby permitting at least some process byproducts produced when a plasma is struck within the plasma processing chamber to adhere to the deposition barrier and reducing the byproduct deposits on the set of plasma processing chamber surfaces.

Methods and arrangement for the reduction of byproduct deposition in a plasma processing system

An apparatus and method for adjusting the voltage applied to a Faraday shield of an inductively coupled plasma etching apparatus is provided. An appropriate voltage is easily and variably applied to a Faraday shield such that sputtering of a plasma can be controlled to prevent and mitigate deposition of non-volatile reaction products that adversely affect an etching process. The appropriate voltage for a particular etching process or step is applied to the Faraday shield by simply adjusting a tuning capacitor. It is not necessary to mechanically reconfigure the etching apparatus to adjust the Faraday shield voltage.

Method for adjusting voltage on a powered Faraday shield

A temperature sensing component enables accurate in situ temperature measurement. The temperature sensing component is disposed within the process chamber. The temperature sensing component has a cavity, in which a transparent cover is disposed over an opening of the cavity. A material is disposed within the cavity of the temperature sensing component, and a sensor is configured to sense a phase change of the material through the transparent cover.

Accurate temperature measurement for semiconductor applications

A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

System and method for surface reduction, passivation, corrosion prevention and activation of copper surface

A system and method for forming a semiconductor in a dual damascene structure including receiving a patterned semiconductor substrate. The semiconductor substrate having a first conductive interconnect material filling multiple features in the pattern. The first conductive interconnect material having an overburden portion. The over burden portion is planarized. The over burden portion is substantially entirely removed in the planarizing process. A mask layer is reduced and a subsequent dielectric layer is formed on the planarized over burden portion. A mask is formed on the subsequent dielectric layer. One or more features are formed in the subsequent dielectric layer and the features are filled with a second conductive interconnect material.

System and method for stress free conductor removal

A method of cleaning a substrate includes receiving a substrate and applying a stress-free cleaning process to the top surface of the substrate. The substrate includes a top surface that is substantially free of device dependent planarity nonuniformities and device independent planarity nonuniformities. The top surface also includes a first material and a device structure formed in the first material, the device structure being formed from a second material. The device structure has a device surface exposed. The device surface has a first surface roughness. A system for stress-free cleaning a substrate is also described.

Methods and systems for a stress-free cleaning a surface of a substrate

A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

System, method and apparatus for improved global dual-damascene planarization

A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

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Fremont, CA, United States of America

Shrikant Lohokare