Enfabrica Corporation

Silicon Graphics, Incorporated

Microsoft Technology Licensing, LLC

Graphics Properties Holdings, Inc.

Shrijeet Mukherjee

Shimon Muller

Rochan Sankar

Ariel Hendel

Thomas James Norrie

Carlo Contavalli

Gurjeet Singh

James E Tornes

Kanoj Sarcar

Frederic Vecoven

Kiran Seshadri

Chetan Loke

Mark Stefan Grossman

Angus Dorbie

Alex Chalfin

Jarrett Redd

David M Blythe

Jeffrey Daudel

Peter Ostrin

John Greth

David G Yu

Jay Peterson

Ari Aravinthan

An adaptive generic receive offload (A-GRO) system and method are disclosed. In some embodiments, the system comprises a host including a host protocol stack and a host memory, and a network interface card that is communicatively connectable to the host. The A-GRO system is configured to: receive a packet from a network, parse the packet to a header and a payload, classify and map the packet into a particular flow based on contexts associated with a plurality of flows and the header, and move the header and the payload to separate queues associated with the particular flow in the host memory, without holding and stalling the packet in hardware of the NIC. By maintain packet coherence information including header chains, the A-GRO allows the host to skip processing the packets between the first and last headers in a GRO aggregation. The A-GRO system also improves mis-ordering packet handling.

System and method for adaptive generic receive offload

A system for congestion control using a flow level transmit mechanism is disclosed. In some embodiments, the system comprises a source SFA and a receive SFA. The source SFA is configured to detect and classify a congestion notification packet (CNP) generated based on congestion in a network; select a receive block from a plurality of receive blocks based on the CNP; forward the CNP to a dedicated congestion notification queue of the receive block; identify a transmit queue from a plurality of transmit blocks based on processing the congestion notification queue, wherein the transmit queue originated a particular transmit flow causing the congestion; and stop the transmit queue.

System and method for congestion control using a flow level transmit mechanism

A system for sharing peripheral component interconnect express (PCIe) devices across multiple host servers is disclosed. In some embodiments, a switch includes a plurality of hosts associated with a plurality of hierarchies, one or more endpoints associated with one or more of the plurality of hierarchies, and a switch communicatively connectable to the plurality of hosts and the one or more endpoints. The switch is configured to: receive a transaction layer packet (TLP); determine a policy group identifier based on parsing and processing the TLP; perform packet forward matching based on the policy group identifier and destination fields of the TLP; based on whether the TLP is communicated between the hosts and endpoints in different hierarchies of the plurality of hierarchies, determine whether to edit the TLP using one or more rewrite rules; and forward the TLP to an appropriate destination link.

System and method for ghost bridging

A system and method for achieving peripheral component interconnect express (PCIe) redundancy and recovery are disclosed. In some embodiments, the system comprises an accelerated compute fabric (ACF) comprising a PCIe switch, an application host communicatively coupled to the ACF using one or more upstream PCIe links, and an endpoint device communicatively coupled to the ACF using one or more downstream PCIe links. The application host is configured to send PCIe transaction layer packets (TLP) addressed to the ghosted endpoint devices through the one or more upstream PCIe links, and the ACF is configured to redirect the PCIe TLP packets to the endpoint device through the one or more downstream PCIe links.

Input/output system interconnect redundancy and failover

A system and method for producing and transmitting reduced data is disclosed. In some embodiments, the system comprises an ACF and reduction processors. The reduction processors are configured to perform a data reduction process. The ACF is configured to obtain access to input data from multiple flows, the input data identified by SGLEs included in input SGLs, and move a portion of the input data from each flow of the multiple flows to a respective reduction processor of the multiple reduction processors, such that each reduction processor receives a respective portion of the input data from each flow. The ACF is further configured to obtain access to reduced data produced from the input data using the data reduction process performed by the multiple reduction processors and move the reduced data to one or more destinations, where the reduced data identified by an output SGL.

NIC based collective acceleration

A system for providing memory access is disclosed. In some embodiments, the system is configured to receive at a source server fabric adapter (SFA), from a server, a memory access request comprising a virtual memory address; using associative mapping, determining whether the virtual address corresponds to a source-local memory associated with the source SFA or to a remote memory. If the virtual address corresponds to the source-local memory, the virtual memory address is translated, at the source SFA, into a physical memory address of the source-local memory. If the virtual address corresponds to the remote memory, a request message is synthesized, and the synthesized request message is transmitted to the destination SFA using a network protocol.

Transparent remote memory access over network protocol

A server fabric adapter (SFA) communication system is disclosed. In some embodiments, the SFA communication system comprises an SFA communicatively coupled to a plurality of controlling hosts, a plurality of endpoints, and a plurality of network ports. The SFA is configured to receive a network packet from a network port of the plurality of network ports; separate the network packet into different portions, each portion including a header or a payload; map each portion of the network packet to: (i) a controlling host of the plurality controlling hosts, the controlling host being designated as a destination controlling host, or (ii) an endpoint of the plurality of endpoints, the endpoint being designated as a destination endpoint; and forward a respective portion of the network packet to the destination controlling host or the destination endpoint.

Server fabric adapter for I/O scaling of heterogeneous and accelerated compute systems

A system for admission and flow control is disclosed. In some embodiments, the system includes a switch for routing network traffic, having multiple classes of service (CoSs), from multiple ingress ports to one or more of multiple egress ports. The system also includes multiple ingress-level class of service queues (InCoS-Qs) and one or more egress-level class of service queues (EgCoS-Qs), each InCoS-Q and EgCoS-Q corresponding to one of CoSs. The switch is configured to detect congestion in a particular EgCoS-Q, corresponding to a particular CoS, the particular EgCoS-Q being associated with a particular host; identify an InCoS-Q corresponding to that particular CoS, and associated with that particular host; and block that InCoS-Q, while allowing routing of the network traffic from one or more InCoS-Qs corresponding to that particular CoS, the one or more InCoS-Qs corresponding to one or more other hosts.

Fine-granularity admission and flow control for rack-level network connectivity

A multi-plane, multi-protocol memory switch system is disclosed. In some embodiments, a memory switch includes a plurality of switch ports, the memory switch connectable to one or more root complex (RC) devices through one or more respective switch ports of the plurality of switch ports, and the memory switch connectable to a set of endpoints through a set of other switch ports of the plurality of switch ports, wherein the set includes zero or multiple endpoints; a cacheline exchange engine configured to provide a data-exchange path between two endpoints and to map an address space of one endpoint to an address space of another endpoint; and a bulk data transfer engine configured to facilitate data-exchange between two endpoints as a source-destination data stream, one endpoint being designated a source address and another endpoint being designated a destination address.

Multi-plane, multi-protocol memory switch fabric with configurable transport

A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system is provided. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

Systems for generating synchronized events and images

A system and method for generating sequences of triggered events and for generating global interrupts in a clustered computer graphics system. In a sender-receiver dichotomy, one node is deemed the sender and the others act as receivers. The sender determines trigger values for each of the nodes in the system in order to achieve a particular operation sequence. In addition, a synchronization signal generator is provided to synchronize a timing signal between the sender and receiver nodes. Further, the sender designates one or more receiver nodes and causes them to turn on an interrupt enable register. In this way, the receiver nodes are able to be interrupted by the sender.

System and method for generating sequences and global interrupts in a cluster of nodes

A system, method, and computer program product is presented for simulating a system of hardware components. Each component is simulated in a hardware definition language such as VERILOG. Each component is represented as a simulated device under test (DUT) that is incorporated into a simulation module. The invention synchronizes the simulation modules by issuing clock credit to each simulation module. Each simulation module can only operate when clock credit is available, and can only operate for some number of clock cycles corresponding to the value of the clock credit. Operation is said to consume the clock credit. After a simulation module has consumed its clock credit, its DUT halts. Once every simulation module has consumed its clock credit and halted, another clock credit can be issued. This allows checkpointing of the operation of each DUT and simulates parallelism of the DUTs using executable images of manageable size. A given DUT can include two or more subsets of logic that each require a clock signal having a different rate. Such subsets of the logic of a DUT are referred to as clock domains. The appropriate clock signals are created by a test bench component of the simulation module. The test bench creates a master clock signal for the DUT. The test bench then divides this clock signal to produce clock signals applied to the clock domains of the DUT. The test bench can be created through automated means by providing a system specification that defines the inputs (including clocks) and outputs of a DUT. This allows a test bench specific to the DUT to be created.

Growing community of inventors

Mountain View, CA, United States of America

Shrijeet Mukherjee