Nvidia Corporation

Mellanox Technologies, Ltd.

Shridhar Rasal

Oren Duer

Liron Mula

Aviv Kfir

Eliav Bar-Ilan

Krishna Kishore Yarlagadda

Karem Kobti

Prateek Patel

Ankit Sharma

Leslin Varghese

Laxman Kumar Dewangan

Disclosed are apparatuses, systems, and techniques that use machine learning techniques for determination and tuning of runtime settings of processing units. In one embodiment, a computing device, which includes one or more processing units, processes, using a machine learning model, a runtime activity data to generate settings for the processing unit(s). The runtime activity data characterizes an execution of a computing application on the processing unit(s). The computing device then modifies, using the generated settings, the execution of the computing application on the processing unit(s).

Optimizing runtime configuration of processing units using machine learning

A computing system includes a volatile memory, a cache coupled with the volatile memory, and a processing device coupled with the cache and at least one of a storage device or a network port. The processing device is to: generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request; allocate, for the data, a continuous range of physical addresses of the volatile memory; generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses; identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and cause the data to be directly stored in the unique cache lines of the cache.

Memory address allocation and cache mapping to retain data in cache

A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the IO request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the IO request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the IO request based on the first timestamp and the second timestamp.

Hardware latency monitoring for memory device input/output requests

One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.

Pacing in a storage sub-system

Growing community of inventors

Pune, India

Shridhar Rasal