Lightspeed Semiconductor Corporation

Adaptec, Inc.

Plantronics, Inc.

Ikoa Corporation

Pmc-Sierra US, Inc.

Aurenta Inc.

Hewlett-Packard Development Company, L.p.

Shridhar K Mukund

Robert Osann, Jr

Anjan Mitra

Lyle Smith

Eric T West

Shafy Eltoukhy

Mahesh Gopalan

Dana How

Adi Srinivasan

Eric F Dellinger

Jung Gu Lee

Sivakumar Munnangi

Neeraj Kashalkar

Pamornpol Jinachitra

Todd Sperry

Patrick Hallinan

Manish Mahajan

Vasantha Srirambhatla

Tvp Kameswar Rao

Jinesh Parikh

Jed Krohnfeldt

Robert Osann

Clement Leung

A head-worn audio device is provided with a circuit for voice signal enhancement. The circuit comprises at least a plurality of microphones, arranged at predefined positions, where each microphone provides a microphone signal. The circuit further comprises a directivity pre-processor and a blind source separation processor. The directivity pre-processor is connected with the plurality of microphones to receive the microphone signals and being configured to provide at least a voice signal and a noise signal. Directivity pre-processing increases the mutual independence of the signals provided to the blind source separation processor and thus improves processing by blind source separation. The blind source separation processor receives at least the voice signal and the noise signal, and is configured to conduct blind source separation on at least the voice signal and the noise signal to provide at least an enhanced voice signal with reduced noise components.

Voice signal enhancement for head-worn audio devices

A headset for acoustic authentication of a user is provided, the headset comprising at least a first microphone, a second microphone, a controllable filter, and an authenticator. The first microphone is arranged to obtain a first input signal. The second microphone is arranged to obtain a second input signal. The controllable filter is configured to receive the first input signal and the second input signal and to determine at least one filter transfer function from the received first input signal and the second input signal. The authenticator is configured to determine a current user acoustic signature from the at least one filter transfer function and to compare the current user acoustic signature with a predefined user acoustic signature and to authenticate the user based on the comparison of the current user acoustic signature with the predefined user acoustic signature.

Headset for acoustic authentication of a user

A method is provided for encoding multiple microphone signals into a composite source-separable audio (SSA) signal, conducive for transmission over a voice network. The embodiments enable the processing of source separation of the target voice signal from its ambient sound to be performed at any point in the voice communication network, including the internet cloud. A multiplicity of processing is possible over the SSA signal, based on the intended voice application. The level of processing is adapted with the availability of the processing power at the chosen processing node in the network in one embodiment. An apparatus for separating out the target source voice from its ambient sound is also provided. The apparatus includes a directed source separation (DSS) unit, which processes the two virtual microphone signals in the SSA representation, to generate a new SSA signal including the enhanced target voice and the enhanced ambient noise.

Method for encoding multiple microphone signals into a source-separable audio signal for network transmission and an apparatus for directed source separation

A method for perceptual enhancement of a received remote talker's voice, in the presence of local ambient noise, in an electronic voice communication system is provided. The method includes generating a pair of binaural voice signals from the remote talker's voice and manipulating the characteristics of the resulting pair of binaural signals. The two ears of the local listener are stimulated binaurally with the pair of binaural voice signals. The stimulating is performed adaptively as the ambient noise in the local listener's environment changes, thereby creating a perception of remote talker reacting actively to the local ambient noise, in a psycho-acoustically pleasing manner to the local listener.

Psycho-acoustic noise suppression

A method for simulating a chip is provided. The method initiates with defining a library of components for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated by combining the library of components and the interconnections for the set of pipelined processors. Then, a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared to the signals generated by the processor circuit. If the comparison of the signals is unacceptable, then the method includes identifying a cause of the unacceptable comparison of the signals at a block level of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.

Simulation of complex system architecture

A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

Networked processor for a pipeline architecture

A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable, in-memory processing semiconductor device

A network node is disclosed. The network node includes a host processor. The network node also includes an integrated circuit. The integrated circuit includes a hardware portion configured to perform a first set of TCP acceleration tasks that require a first speed level. The integrated circuit also includes a network protocol processor configured to perform a second set of TCP acceleration tasks that require a second speed level, which is lower than the first speed level. The integrated circuit further includes an embedded processor configured to perform a third set of TCP acceleration tasks that require a third speed level, which is lower than the second speed level. The network node further includes a plurality of data paths configured to couple the integrated circuit to the host processor, the plurality of data paths being implemented based on different protocols.

Systems and methods for implementing host-based security in a computer network

An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data paths. The plurality of access data paths are also configurable for a write access from one of the plurality of access data paths. The multi-level array is capable of being configurable into logical partitions with arbitrary starting addresses. The apparatus further includes a compute element in communication with the multi-level array over the plurality of access data paths, the compute element configured to issue a plurality of memory accesses to the multi-level array through the plurality of access data paths. Methods for programming a multi-level array of storage cells and for processor design are also provided.

Apparatus for performing computational transformations as applied to in-memory processing of stateful, transaction oriented systems

A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems

A method for efficiently processing layers of a data packet is provided. The method initiates with defining a pipeline of processors communicating with a distributed network and CPU of a host system. Then, a data packet from the distributed network is received into a first stage of the pipeline. Next, the data packet is processed to remove a header associated with the first stage. Then, the processed data packet is transmitted to a second stage. The operations of processing and transmitting the processed data packet are repeated for successive stages until a header associated with a final stage has been removed. Then, the data packet is transmitted to the CPU of the host system. It should be appreciated that the header is not necessarily transformed at each stage. For example, suitable processing that does not strip the header may be applied at each stage.

Method and apparatus for a pipeline architecture

A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second operand has a greater bit width than the first operand. Next, the first operand is transformed by aligning a least significant bit of the first operand to a lowest bit position of a transformed operand having a bit size equal to the second operand. Then, the bits of the transformed operand are sign extended and padded in a manner to allow carry propagation. Next, the transformed operand is transmitted to the processor. A method for shifting operands and a processor are also provided.

Method and apparatus for aligning operands for a processor

An architecture for implementing host-based security such that data security may be applied whenever the confidential data leaves a host computer or a networked device. The improved method and architecture may be implemented in a single integrated circuit for speed, power consumption, and space-utilization reasons. Within the integrated circuit, a combination of hardware-implemented, network processor-implemented, and software-implemented functions may be provided. The innovative host-based security architecture may offer line-rate IPSec acceleration, TCP acceleration, or both.

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San Jose, CA, United States of America

Shridhar K Mukund