International Business Machines Corporation

Shricharan Srivatsan

Vivek Britto

Tharunachalam Pindicura

Aishwarya Dhandapani

John Andrew Schumann

Yan Xia

Brian William Thompto

Karen E Yokum

Bryant Cockcroft

Madhumitha Venkataraman

A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

Method for latency detection on a hardware simulation accelerator

Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

Detecting deviations from targeted design performance in accelerator/emulator environment

A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.

Reducing the memory load time for logic simulator by leveraging architecture simulator

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.

Performance benchmark generation

Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.

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Austin, TX, United States of America

Shricharan Srivatsan