Samsung Electronics Co., Ltd.

Shreyas Samraksh Jayaprakash

Parvinder Kumar Rana

Abhishek Ghosh

Shyam Agarwal

Sandeep B V

Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

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Karnataka, India

Shreyas Samraksh Jayaprakash