Xilinx, Inc.

Shreyas Manjunath

Mrinal J Sarmah

Prasun K Raha

Rajeev Patwari

Vamsi Krishna Nalluri

Sai Lalith Chaitanya Ambatipudi

Sandeep Jayant Sathe

Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

Compression of sparse tensors

A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

System and method for device synchronization

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San Jose, CA, United States of America

Shreyas Manjunath