Qualcomm Incorporated

Shreepad Amar Panth

Yang Du

Kambiz Samadi

Robert P Gilmore

Pratyush Kamal

Jing Xie

A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro

A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace

Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Clock distribution network for 3D integrated circuit

The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

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Atlanta, GA, United States of America

Shreepad Amar Panth