Taiwan Semiconductor Manufacturing Comp. Ltd.

Virage Logic Corporation

Shreekanth Sampigethaya

Bharath Upputuri

Subramani Kengeri

Deepak Sabharwal

Niranjan Behera

Prakash Ravikumar Bhatia

Sanjiv Kainth

A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.

Offset compensation for sense amplifiers

A method of re-offsetting a plurality of amplifier is provided. The method includes testing the plurality of amplifiers based on a re-offset value at bulks of compensation transistors of the plurality of amplifiers; identifying a first group of first amplifiers of the plurality of amplifiers favoring reading a first logic level and/or a second group of second amplifiers of the plurality of amplifiers favoring reading a second logic level different from the first logic level, based on results of the testing step; changing the re-offset value to a new re-offset value; re-offsetting the first group of first amplifiers and/or the second group of second amplifiers based on the new re-offset value; and re-testing the first group of first amplifiers and the second group of second amplifiers.

A method of controlling a plurality of memory cells in a row. The method includes controlling a switching element using at least one write word line signal to raise a voltage of a node connected to the plurality of memory cells in the row when the plurality of memory cells in the row operate in a first mode. The method further includes controlling at least one transistor using the at least one write word line signal to connect the plurality of memory cells in the row to a reference voltage when the plurality of memory cells in the row operate in a second mode.

Memory cells having a row-based read and/or write support circuitry

A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages.

A circuit comprises a plurality of memory cells in a row, at least one write word line, and a write support circuit coupled to the at least one write word line and to the plurality of memory cells in the row. The write support circuit includes a first current path and at least one second current path. A current path of the at least one second current path corresponds to a respective write word line of the at least one write word line. A write word line of the at least one write word line is configured to select the first current path when the plurality of memory cells in the row operates in a first mode, and to select a second current path of the at least one second current path when the plurality of memory cells in the row operates in a second mode.

A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

Multi-port memory utilizing an array of single-port memory cells

An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.

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San Jose, CA, United States of America

Shreekanth Sampigethaya