Matsushita Electric Industrial Co., Ltd.

Shozo Okada

Naoto Matsuo

Yoshiro Nakata

Toshiki Yabu

Susumu Matsumoto

Hisashi Ogawa

Michihiro Inoue

Hiroyuki Sakai

Masaaki Niwa

Shuichi Kameyama

Masanori Fukumoto

Yasushi Naito

Kazuhiko Tsuji

Kazuhiro Matsuyama

Kazuhiro Kobushi

A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

Semiconductor memory device in which a capacitor electrode of a memory

A semiconductor memory device is provided which includes a semiconductor substrate of a first conductivity type, a plurality of trench capacitors formed in the substrate and a plurality of switching transistors formed on the respective trench capacitors. Each of the switching transistors is electrically connected to the corresponding trench capacitor. Each of the trench capacitors has a first electrode formed in the side portion of a trench provided in the substrate and a second electrode containing impurities of the first conductivity type and embedded in the trench. Each of the switching transistors has a source region formed from a first epitaxial layer of the first conductivity type grown on the trench so as to electrically contact the second electrode, a channel region formed from a second epitaxial layer of a second conductivity type grown on the first epitaxial layer, and a drain region formed from a third epitaxial layer of the first conductivity type grown on the second epitaxial layer. The first, second and third epitaxial layers are in contact with a polycrystalline silicon layer containing impurities of the second conductivity type. The first conductivity type is opposite to the second conductivity type.

Method of producing a semiconductor device having trench capacitors and

A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.

Semiconductor memory device and a manufacturing method thereof

In a method for manufacturing DRAMs in a stacked memory cell type, an edge portion of each bit line is bared upon etching a first insulating film, the bared edge portion is etched to from an opening and an inner peripheral surface of the opening is covered by a second insulating film. There is also disclosed a method wherein second and third insulating films and second conductive film are stacked on a first insulating film, a second conductive film is formed and the second conductive film and the first conductive film are partially etched whereby the unetched portions of the first conductive film serve as electrode planes of charge storage electrodes.

Method for manufacturing a semiconductor memory device

A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.

Dram with concentric adjacent capacitors

Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

Method for making semiconductor integration circuit with stacked

A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

Thin-film semiconductor device and method of fabricating the same

There is provided a method for determining the presence of an insulating film on the surface of an electrically conductive material. In this method, an electrically conductive probe is brought into contact with the surface of a specimen, and a voltage is applied between the probe and the surface of the specimen. A tunneling current which flows through the probe is detected and amplified, while controlling the distance between the probe and the surface of the specimen to ensure a substantially constant tunneling current.

Method for determining the presence of thin insulating films

Semiconductor memory device and a method for producing the same

Disclosed is a semiconductor memory device comprising a semiconductor substrate on which memory cells are formed, each including a switching transistor formed on the semiconductor substrate and a capacitor disposed above the switching transistor. The capacitor has a storage electrode, a cell plate and a capacitor insulating film sandwiched therebetween. The storage electrodes of at least two adjacent memory cells are partly disposed one above the other, with part of the cell plate interposed therebetween. Also disclosed is a semiconductor memory device in which the capacitors of the memory cells are disposed in a trench formed in the semiconductor substrate. The two switching transistors of two adjacent memory cells are located on each island-shaped active region surrounded by the trench. The storage electrodes of the capacitors of the two adjacent memory cells extend side by side around the corresponding active region, with part of the cell plate interposed between the storage electrodes.

Semiconductor memory device

Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

Growing community of inventors

Kobe, Japan

Shozo Okada