Kabushiki Kaisha Toshiba

Other

Shozo Nitta

Yasuhiro Sugimoto

Akira Morikawa

Kenji Tanaka

Sean Chuang

Tatsuo Isumi

Mike Koen

Kyoji Matsusako

A front end signal processing method and apparatus for processing a signal from an image sensor are provided for readily clamping a black level, improving the manufacturing yield, and reducing the power consumption. A luminance detector/digitizer receives a sensor output signal from an image sensor, detects luminance information included in the sensor output signal, and generates a digital luminance signal representative of the detected luminance information. A digital processor receives the digital luminance signal, and multiplies the digital luminance signal by a predetermined gain code to generate the multiplication result as a front end processed signal output. An optical black clamp receives the digital luminance signal from the luminance signal detector/digitizer and supplies a feedback signal produced from the digital luminance signal to the luminance signal detector/digitizer to clamp a black level of the luminance signal to a constant value.

Method and apparatus for processing front end signal for image sensor

The timings can be generated in synchronism with master clocks, so that it is possible to obtain the timing generating device of synchronous circuit, which is effectively applicable to a large scale integrated circuit, while facilitating the test thereof. Addresses A [0, m-1] are given to the register 1 in synchronism with the input pulses CLK; delay data D [0, n-1] are read from the memory device 3 on the basis of the outputs of the register 1; the delayed data are stored in the registers 4-1 to 4-k independently on the basis of the distributive pulses CK1 to CKk applied by the pulse distributing circuit 2 for distributing the input pulse CLK to a plurality of routes in sequence; the data signals S1i to Ski obtained by the registers 4-1 to 4-k are given to the delay circuits 6-1 to 6-k through the DA converters 5-1 to 5-k to control the delay times in such a way that the distributive pulses CK1 to CKk can be controllably delayed by the delay circuits 6-1 to 6-k; and the obtained delay pulses CK1X to CKkX are outputted through the OR gate 7 as a continuous pulse train.

Timing generating device

A differential RS latch circuit has a series structure wherein a first differential transistor pair, a second differential transistor pair and a third differential transistor pair are connected in three stages, and jointly function as one current switch. A first diode serving as a first level shift element is provided in a first current path between a power source node and a grounding node, and second and third diodes serving as second and third level shift elements are provided in a second current path between the power source node and the grounding node. The number of elements provided in the first current path is equal to that of elements provided in the second current path. As a result, the first and second current paths are equal to each other in response speed to a signal, and thus an hazard is prevented from occurring even at the time of the switching operation between the first and second current paths.

Differential RS latch circuit

A bias current supplying circuit having: a differential amplifier for amplifying a difference between potentials at first and second nodes and outputting the amplified difference voltage from a third node, the first node being connected to an output terminal of a bias voltage source for outputting a bias voltage, and the second node being connected to an output terminal from which a bias current is supplied to an external circuit; a negative feedback loop circuit for changing the potential at the second node in accordance with the potential at the third node of the differential amplifier; and a potential dropping circuit connected to the second node for dropping the potential at the second node in response to an external input of a control signal and intercepting a supply of the bias current to the external circuit.

Bias current supplying circuit

According to this invention, a level converter has a pair of differential transistors operated at a negative voltage in accordance with an ECL-level input signal, and first and second output nodes are arranged between a collector of one transistor of the pair of differential transistors and a positive power source voltage. A level-converting resistor for converting an ECL-level signal to a positive level signal is inserted between the first output node and the second output node so as to output the positive level signal in accordance with an ECL-level input signal to the first output node. The emitter-collector path of a bipolar transistor is inserted between the second output node and the positive power source voltage. A clamp potential for controlling saturation of transistors constituting a TTL circuit connected to an output of the transistor is generated by a constant potential applied to the base of the transistor.

Growing community of inventors

Tokyo, Japan

Shozo Nitta