Nec Corporation

Shozo Nishimoto

Yasukazu Inoue

Hiroshi Kotaki

In a method for manufacturing a semiconductor device, layer including a first portion having a first height and a second portion having a second height different from the first height is formed on a substrate. Then, an image formation beam is irradiated onto the layer to form first and second patterns on the first and second portions, respectively. A minimum feature size of the first pattern is different from that of the second pattern.

Method for manufacturing pattern layer having different minimum feature

A method of processing an insulating film containing voids associated with the increased semiconductor device density is performed. An insulating film containing voids is coated with another insulating film by spin-on technique to substantially close up the voids, followed by photolithography process. By the processing without adverse affects from the presence of voids, for example, an undamaged cover film can formed, which can contribute to greater reliability of semiconductor devices.

Process of fabricating a dielectric film for a semiconductor device

A semiconductor memory device having a memory cell including a transistor having, as source and drain regions, impurity-diffused regions formed selectively in the active area isolated by field insulating film formed selectively at the surface of a semiconductor substrate and a capacitor comprising a lower electrode including a bottom electrode and a cylindrical electrode. The bottom electrode is formed on an interlayer insulating film formed over the substrate and is connected to one of the impurity-diffused regions through a first hole opened in said interlayer insulating film. The cylindrical electrode is formed at the edge portion of said bottom electrode and a plurality of second holes formed in the interlayer insulating film on said field insulating film. The first hole and the second holes have substantially the same dimensions except for a depth thereof. The second holes are arranged to be a mark representing characters to assist the process control. In addition, a check element fabricated by forming the lower electrodes covering a plurality of second holes and cylindrical electrodes so that these electrodes assume a loop toothed at a certain pitch can be prevented from being broken down even if the dimensions are large.

Semiconductor memory device

A wiring layer structure of a resin sealed semiconductor integrated circuit, which is free from slide of wiring layer during heat cycle test, is disclosed. The slide is prevented by making an effective width of the wiring layer smaller by means of slits formed in the wiring layer. A reduction of area to be occupied by the wiring layer is realized by reducing a total width of the wiring layers by increasing the density of slits with increase of a distance from a corner of the chip.

Resin sealed semiconductor integrated circuit

A semiconductor device has a device section and a peripheral section outside the device section. A main vernier pattern is formed in the peripheral section for inspecting finely an alignment state in a first direction, and a subsidiary vernier pattern is formed in the peripheral section near the main vernier pattern for inspecting coarsely an alignment state in a second direction at a right angle to the first direction.

Method of manufacturing a semiconductor device using a main vernier

A dynamic random access memory device including one-transistor type memory cells each having a trench capacitor is disclosed. An impurity region of a conductivity type opposite to the substrate and having a net-like plane shape is provided in an inner portion of the substrate, and the impurity region is led-out at a part to the major surface of the substrate. A trench is formed in the substrate from the major surface into the impurity region so that a wall section of the trench is constituted by the impurity region. A dielectric film of the capacitor is formed on the wall section, and a capacitor electrode is formed on the dielectric film and connected to source or drain region of the transistor.

Dynamic random access memory device having a plurality of improved

A semiconductor integrated circuit device having a flip-flop circuit with first and second insulated gate field effect transistors is disclosed. The gate electrode of the first transistor is connected to one impurity region of source and drain regions of the second transistor, and the gate electrode of the second transistor is connected to one impurity region of source and drain regions of the first transistor. A part of the one impurity region of the first transistor and a part of the one impurity region of the second transistor are overlapped each other with an insulating film being interposed therebetween to form a capacitor element by using the impurity regions as upper and lower electrodes, respectively, and the insulating film as a dielectric film.

Growing community of inventors

Tokyo, Japan

Shozo Nishimoto