Spansion Llc.

Fujitsu Corporation

Shozo Kawabata

Takaaki Furuyama

Kenji Shibata

Satoru Kawamoto

Masaya Katayama

Kenta Kato

Masaki Ito

Mitsuhiro Nagao

Sooyong Park

A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

Method and apparatus for address allotting and verification in a semiconductor device

The control method includes a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within a memory block.

Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is varied

The semiconductor device comprises a first wellof a first conduction type formed in a semiconductor substrate; a second wellof a second conduction type formed in the first well; and a transistorincluding a control gateformed of an impurity region of the first conduction type formed in the second well, a first impurity diffused layerand a second impurity diffused layerformed with a channel regiontherebetween, and a floating gate electrodeformed on the channel regionand the control gatewith a gate insulation filmtherebetween. The control gateis buried in the semiconductor substrate, which makes it unnecessary to form the control gateon the floating gate electrode. Thus, the memory transistor and the other transistors, etc. can be formed by the same fabricating process. Thus, the fabrication processes can be less and the semiconductor device can be inexpensive.

Method for fabricating a semiconductor device

When an initializing operation starts, a busy state indicative of the disenable of access operation is set (S), and read operation information is read out by preferentially using a verify sense amplifieror a high-speed read sense amplifier(S). Upon completion of latching the read operation information (S: Y), a ready state that announces that the read access operation from a non-redundant memory region is enabled is set (S), and a ready signal is outputted according to an external read access request to the non-redundant memory region. A boot program or the like which is in the non-redundant memory region can be read out in parallel with the read of the operation information. Subsequently, the redundancy information is read out (S), and a ready state that announces that the read access operation from all of the memory regions is enabled is set upon completion of reading out the redundancy information (S). Thereafter, rewrite operation information is read out (S). The period of time since the start of the initializing operation to the start of the read access operation can thereby be reduced.

Method and apparatus for initialization control in a non-volatile memory device

A verify sense amplifier () reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (). Upon completion of rewriting, the comparator circuit () outputs a match signal MCH. A selector () outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier () is stored in the volatile data retaining unit (). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit () upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

Method and apparatus for setting operational information of a non-volatile memory

Semiconductor device comprising transistors having control gates and floating gate electrodes

It is intended to provide control method and a nonvolatile semiconductor memory device capable of erase operation or write operation in high speed securing reliability without applying excessive electric field. An operation unit consists of a plurality of operation cycles each of which has a bias-application period and a verification period. Addition voltage &#x394;V is added to each operation unit as bias voltage, whereby a write operation can be carried out with characteristic of injected current IFG that is uniform among respective operation units duration of which are generally same. In this case, duration of operation cycles are shortened by each operation unit and duration of verification periods are shortened so as to avoid a situation such that a write operation completes in the middle of a bias-application period and after that, another write operation continues to cause excessive voltage stress on non-volatile semiconductor memory cells.

Growing community of inventors

Kasugai, Japan

Shozo Kawabata