Matsushita Electric Industrial Co., Ltd.

Shozo Fujii

Yoshio Sakakibara

Hideki Ohtaka

Atsushi Hashimoto

Takao Kashiro

Kazuhiko Kobayashi

Makoto Mitsuda

Masafumi Sato

Katuji Uro

A video signal processing apparatus comprising an oscillating unit for outputting a signal of a stable frequency, a counting unit for counting the period of a cycle of a signal supplied from the outside based on the signal output by the oscillating unit, a clock number calculating unit for calculating the number of clocks in a line based on a result of counting by the counting unit, a comparing unit for comparing the number of clocks calculated by the clock number calculating unit with a threshold to decide which is larger, a switching unit for deciding the number of clocks in the next operation by switching to the number of clocks calculated by the clock number calculating unit if the calculated number of clocks is larger than the threshold, or deciding the number of clocks in the next operation by holding the number of clocks in a line in the current operation as it is, and a synchronizing signal generating unit for, based on the number of clocks in operation decided by the switching unit and the signal output by the oscillating unit, generating a synchronizing signal for a video signal, thereby preventing a shake of a frame signal supplied from the outside from directly affecting a synchronizing signal to be generated for a video signal so that a visually adverse shake of image on a TV screen can be suppressed.

Video signal processing apparatus

There is provided a data memory apparatus which can efficiently use a general-purpose DRAM as a memory used during the digital data error correcting and modifying processing. The apparatus is comprised of a DRAM, a DRAM access unit and an error correcting circuit. Input digital data is first subjected to the error correcting processing by means of the error correcting circuit, assigned with a result of the error correcting processing and transferred to the DRAM access unit. The DRAM access unit accesses the DRAM in a page mode to store the data in the DRAM.

Data memory apparatus

A helical scan type digital recording/reproducing apparatus arranged such that data corresponding to m fields/frames are divisionally recorded in n tracks on a magnetic tape and a slow, still or frame advance reproduction mode is effected in response to an instruction from an external input. The apparatus is equipped with a signal processing circuit coupled to a rotary head for inputting data reproduced from the magnetic tape by the rotary head to store the reproduced data in a memory. In response to the instruction for the slow, still or frame advance reproduction mode, the signal processing circuit outputs a control signal when the data corresponding to one or more frames/fields are stored in the memory. Also included is a servo circuit coupled through a signal line to the signal processing circuit to be responsive to the control signal from the signal processing circuit. The servo circuit controls a capstan motor in accordance with the control signal and the reproduction mode instruction.

Apparatus for recording/reproducing digital data on/from recording medium

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Hirakatashi, Japan

Shozo Fujii