Renesas Electronics Corporation

Nec Electronics Corporation

Shouzou Uchida

Hiroshi Furuta

Muneaki Matsushige

Junji Monden

Satoshi Yamamoto

Hideo Inaba

Masatoshi Sonoda

Yoshiyuki Katou

A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.

Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error

A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.

A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer. Different signals are input to each of the gate electrodes, the substrate potential diffusion layer or the well potential diffusion layer are formed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor.

Semiconductor integrated circuit device

The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell arrayThen, a test signal TEis set '1' to set a device in a test mode. Refresh addresses for test are then stored in a data store circuitA first address for test is applied to an address terminalwhereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell arrayare checked to decide the presence or absence of any abnormality.

Growing community of inventors

Kanagawa, Japan

Shouzou Uchida