Sino Ic Technology Co., Ltd.

Shouyin Ye

Hua Wang

Jie Zhang

Bin Luo

Jianhua Qi

Zhiyong Zhang

Jianbo Ling

Xuefei Tang

Jianming Ye

A configuration and testing method and system for an FPGA chip using a bumping process are disclosed, the method includes creating configuration files for an FPGA chip under test and storing them in a memory; reading, by a master FPGA, a configuration code stream of corresponding configuration codes from the mass memory, configuring the FPGA chip under test via an external test interface, and determining whether the configuration is successful; if the configuration is successful, converting the configuration code stream into a test signal source file that is recognizable, executable and reusable by multiple pieces of test equipment by a developed algorithm and a conversion tool; and automatically loading the test signal source file onto the FPGA chip under test in real time by advanced test equipment.

Configuration and testing method and system for FPGA chip using bumping process

A test apparatus with physical separation feature is disclosed. The test apparatus includes probes (), a peripheral circuit (), a circuit of special function (), wherein the peripheral circuit and the circuit of special function are separately arranged on different circuit boards (). The peripheral circuit and the circuit of special function are both electrically connected to the probes. In the test apparatus with physical separation feature, the peripheral circuit and the circuit of special function are separated in physical spaces, so that interference between the components is prevented and the testing cost is reduced.

Test apparatus with physical separation feature

Growing community of inventors

Pudong New Area, China

Shouyin Ye