Tsinghua University

Intel Corporation

Southeast University

Beijing Superstring Academy of Memory Technology

Other

Beijing Tsingmicro Intelligent Technology Co., Ltd.

Shouyi Yin

Shaojun Wei

Leibo Liu

Dawei Wang

Jiqiang Song

Eugene Tang

Bo Wang

Longxing Shi

Jun Yang

Peng Cao

Bo Liu

Ao Luo

Jianfeng Zhu

Guiqiang Peng

Jinjiang Yang

Lei Zhang

Min Zhu

Xiao Yang

Sun C Chan

Kai Zhou

Peng Ouyang

Ao Qiong Li

Jesse Z Fang

Yang Xue

XiangYu Kong

Zhaoshi Li

Randolph Wang

Shibin Tang

Paul Peng

Baofen Yuan

Yansheng Wang

Xiudong Li

A method for a compilation, an electronic device and a readable storage medium are provided. The method for a compilation includes analyzing source program data to determine a target irregular branch, generating an update data flow graph according to the target irregular branch, and mapping the update data flow graph to a target hardware to complete the compilation.

Method for compilation, electronic device and storage medium

An image correction method includes: capturing speckle patterns on two planes at different distances to obtain a first image of speckle projected on a first plane and a second image of speckle projected on a second plane; matching the first image with the second image to obtain sub-pixel matching points; obtaining, based on first physical coordinates of the sub-pixel matching points on the first image and second physical coordinates of the sub-pixel matching points on the second image, a mapping matrix between the first and second physical coordinates; obtaining a direction vector of a center of the speckle projector in a camera reference frame according to the mapping matrix; adjusting coordinate axis directions of the camera reference frame to align a horizontal axis direction with the direction vector, updating an imaging matrix of the camera; and mapping a target scene image through the imaging matrix to obtain a corrected image.

Image correction method and apparatus for camera

A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

Voter-based method of controlling redundancy, electronic device, and storage medium

The disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring a first access record of the processor to a first memory during a running process, the first access record including reading-operation information; acquiring a second access record of a checking device to a second memory during a replay process, the second access record including first reading-operation information, the first reading-operation information being reading-operation information corresponding to a case in which a first access of the checking device to a same address during the replay process is a reading operation, and determining, based on the first access record and the second access record, whether or not the processor reads during the running process a memory address that is not any one of addresses included in the second access record.

Processor checking method, checking device and checking system

The present disclosure provides a processor checking method, a checking device and a checking system. The method includes acquiring an access record to a memory by a processor during a running process, the access record includes a read operation information and a corresponding time information, determining whether there is a read operation information corresponding to a high access authority in the access record, and when there is a read operation information corresponding to a high access authority, determining whether the read operation information corresponding to the high access authority belongs to an unauthorized operation. According to embodiments of the present disclosure, the behavior of the processor reading data from the memory is checked and analyzed, thereby preventing the security problems caused by malicious use of unauthorized reading operation.

Provided is a method for generating configuration information of a dynamic reconfigurable processor. The dynamic reconfigurable processor includes a processing unit array, and the processing unit array includes a plurality of processing units. The method includes steps of: reading information of a task to be executed and generating an array configuration information top of the processing unit array according to the information; generating a plurality of processing unit configuration information corresponding to the plurality of processing units respectively according to the information; and assembling the array configuration information top and the plurality of processing unit configuration information.

Method and device for generating configuration information of dynamic reconfigurable processor

A reconfigurable processor and a conditional execution method for the same are provided. The reconfigurable processor includes: a routing unit, configured to assign a conditional judgment statement and a conditional execution statement to process the conditional judgment statement and the conditional execution statement in parallel; a first arithmetic logic unit, configured to process the conditional judgment statement according to an assignment of the routing unit to obtain a single-bit signal; a second arithmetic logic unit, configured to: process the conditional execution statement according to the assignment of the routing unit to obtain a conditional execution result; receive the single-bit signal; and control an output of the conditional execution result according to the single-bit signal. The reconfigurable processor according to embodiments of the present disclosure may reduce a dependence distance and a running time of the conditional branch statement and enhance an execution efficiency of the conditional branch statement by executing the conditional judgment statement and the conditional execution statement in parallel.

Reconfigurable processor and conditional execution method for the same

The present invention discloses an INS network-based anti-fault attack method of random infection, comprising the steps of sending the plain-text into an encryption processor, wherein two groups of cipher text are outputted through temporal or spatial redundancy; conducting XOR operation) on the two groups of said cipher text output to obtain the output difference; sending the said output difference into an infection function module to initiate an infection operation to obtain the infection result; conducting XOR operation on any of said groups of cipher text output to generate the final output. The present invention can realize the randomization of infection function in infection countermeasures, reduce the successful probability of fault attack and improve the safety of the circuit.

One INS network-based anti-fault attack method of random infection

A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.

Extending the capabilities of existing devices without making modifications to the existing devices

A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration management unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

Cache structure and management method for use in implementing reconfigurable system configuration information storage

A signal detecting method and device are disclosed. The method includes: obtaining a matched filtering signal; determining a filtering matrix; decomposing the filtering matrix to obtain a principal diagonal matrix and a non-principal diagonal matrix; obtaining a parameter matrix and a parameter vector according to the principal diagonal matrix, the non-principal diagonal matrix, and the matched filtering signal; obtaining an iterative parameter and an iterative initial value according to the parameter matrix and the parameter vector; and performing an iterative calculation according to the iterative parameter and the iterative initial value; if the number of iterations reaches a preset number, obtaining an iterative final value, and obtaining an input of a decoder according to the iterative final value. The signal detection method may reduce the computational complexity and bit error rate, improve data throughput, and more advantageous for use in a large-scale multi-input multi-output system.

Signal detecting method and device

Disclosed are a pre-decoding analysis-based configuration information cache management system, comprising a streaming media processing module, a configuration information prefetch FIFO module, a configuration information storage unit, and a cache controller module. Also disclosed is a management method for the pre-decoding analysis-based configuration information cache management system. The present invention allows for increased dynamic reconfiguration efficiency of a large-scale coarse-grained reconfigurable system.

Pre-decoding analysis based configuration information cache management method and system

An apparatus, method and system are provided to allow a low power and fast application service transmission (LP-FAST) engine to enhance the quality of service (QoS) and optimize the power consumption of the mobile applications operating in a mobile terminal in a service-aware, bandwidth-aware and power-consumption-aware manner.

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Beijing, China

Shouyi Yin