Silicon Laboratories Inc.

The University of Texas System

Intellectual Ventures Holding 81 LLC

Shouli Yan

Axel Thomsen

Xiaodong Wang

Mohamed M Elsayed

Zhiwei Dong

Ka Yin Leung

Matthew Powell

Zhiheng Cao

William W K Tang

Yan Zhou

Alan Lee Westwick

Jinwen Xiao

Clayton H Daigle

Praveen Kallam

Gang Yuan

Michael D Bryant

Benito R Fernandez

Brian R Remy

Xiaohong Li

A voltage regulator circuit with variable feedback is disclosed. In one embodiment, a voltage regulator includes an amplifier having a first input configured to receive a reference voltage and a second input configured to receive a feedback signal. The voltage regulator further includes first and second transistors each having respective gate terminals coupled to an output of the amplifier. A resistor network coupled to the second input of the amplifier and further coupled to the first and second transistors. The resistor network is configured to produce the feedback signal based on currents through the first and second transistors, respectively.

Voltage regulator with adjustable feedback

An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.

Apparatus for offset correction in electronic circuitry and associated methods

A method includes using a pass device of a linear regulator to provide an output signal to an output of the linear regulator in response to a signal that is received at a control terminal of the pass device. The method includes using the linear regulator to regulate the signal received at the control terminal based at least in part on the output signal; and controlling a closed loop frequency response of the linear regulator to cause a direct current (DC) gain of the linear regulator to extend to a frequency near or at frequency of a zero that is associated with a decoupling capacitor that is coupled to the output of the linear regulator.

Linear regulator having a closed loop frequency response based on a decoupling capacitance

In an embodiment, an apparatus may include an amplifier circuit including a first input to receive a signal, a second input to receive a feedback signal, and an output. The apparatus may further include a buffer circuit including an input coupled to the output of the amplifier and including an output coupled to an output node. The apparatus may also include a feedback circuit coupled between the output node and the second input of the amplifier circuit. The feedback circuit may include at least one non-linear resistor configured to define a feedback ratio that changes in response to a voltage at the output node.

Reference buffer circuits including a non-linear feedback factor

A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.

Multi-stage sample and hold circuit

A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.

Dual-path comparator and method

A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.

Method and apparatus for calibration of successive approximation register analog-to-digital converters

A circuit includes a comparator including a first input, a second input, and an output. The circuit further includes a plurality of capacitive sampling circuits configured to be selectively coupled to the first and second inputs. Each of the plurality of capacitive sampling circuits includes first and second capacitors, and includes first and second conversion switches configured to selectively couple the first and second capacitors to the first and second inputs, respectively. The first and second conversion switches of a selected one of the plurality of capacitive sampling circuits are closed to couple the selected one to the first and second inputs of the comparator during a conversion phase.

Successive approximation register analog-to-digital converter with multiple capacitive sampling circuits and method

A voltage reference circuit includes a capacitor including a first terminal and including a second terminal coupled to a power supply node. The voltage reference circuit further includes an amplifier, a first transistor, and a switch. The amplifier includes a first input configured to receive a reference voltage input signal, a second input configured to receive a feedback signal, and an output. The first transistor includes a source coupled to the second input of the amplifier and to an output node, a gate coupled to the capacitor, and a drain. The first transistor is configured to provide a reference voltage at the source based on a charge provided to the gate by the capacitor. The switch includes a first terminal coupled to the output of the amplifier, and includes a second terminal coupled to the first terminal of the capacitor.

Clocked reference buffer in a successive approximation analog-to-digital converter

A digital-to-analog converter (DAC) with a digital segment having a digital data input and an analog segment coupled to the digital segment and having an analog output to output an analog signal corresponding to the digital data. The analog segment includes one or more gain stages and a feedback structure to couple the analog output to the one or more gain stages to attenuate signal distortion at the analog output. A combined gain of the one or more gain stages determines a signal distortion attenuation characteristic of the analog segment.

Low-power digital-to-analog converter

A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical 'low' or a logical 'high' voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical &#x201c;low&#x201d; voltage level or the logical &#x201c;high&#x201d; voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical &#x201c;low&#x201d; voltage level and the logical &#x201c;high&#x201d; voltage level.

Schmitt trigger with gated transition level control

An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link. A differential transmitter on each of the plurality of communications channels transmits the data on the first link at a selected one of a first phase and a second phase and for transmitting the data on the second link at the selected one of the first phase and the second phase. The second phase is 180 degrees out of phase with the first phase. Each of the differential transmitters controls the selection of the first phase and the second phase on each of the first link and the second link such that only the first phase or the second phase is cross coupled onto a selected communications channel from adjacent communications channels.

Capacitive isolation circuitry

An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level.

Capacitive isolation circuitry with improved common mode detector

A low-power switched-capacitor circuit is disclosed. The low-power switched-capacitor circuit includes a p-channel switched-capacitor integrator and an n-channel switched-capacitor integrator. The p-channel switched-capacitor integrator includes a first set of input transistors controlled by a first set of capacitors and switches. The n-channel switched-capacitor integrator includes a second set of input transistors controlled by a second set of capacitors and switches. The p-channel switched-capacitor integrator and the n-channel switched-capacitor integrator function together in a push-pull fashion such that a required transconductance as well as width and drain current of the first and second sets of input transistors are reduced by half of those in a conventional switch-capacitor circuit.

Switched-capacitor circuit

A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, F, F, F, F, Fof a Taylor series equation and calculates distance functions. The digital processor also includes a digital register for storing a magnitude scaling factor &#x3c6;(x,y) of the Taylor series equation. The DAC control register uploads a lead term F(x,y) of the Taylor series equation from the digital processor to the DAC. The first-order digital registers controls resistances of the R2R ladders. The second-order digital registers uploads coefficients F, F, F, F, Fof the Taylor series equation from the digital processor to the DAC. The analog integrator adds outputs from the DAC and the R2R ladder to generate approximation results for the Taylor series equation.

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Austin, TX, United States of America

Shouli Yan