Fujitsu Corporation

Fujitsu Microelectronics Limited

Shouji Sakuma

Yoshiyuki Ishida

Shinji Fukasawa

A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.

Wafer structure with a plurality of functional macro chips for chip-on-chip configuration

A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the wiring as a delay element to eliminate hold errors from the scan chain. This method eliminates hold errors from the data holding circuits. This keeps the number of buffer circuits inserted between the data holding circuits small and shortens the processing time required for correcting the hold error.

Growing community of inventors

Kasugai, Japan

Shouji Sakuma