Macronix International Co., Ltd.

Shou-Wei Huang

Chien-Hung Liu

Shyi-Shuh Pan

Ying-Tso Chen

Tung-Cheng Kuo

Erh-Kun Lai

Chin-Hsien Chen

Chin-Cheng Yang

Hsin-Huei Chen

Cheng-Wei Lin

Yu-Ping Huang

Guan-De Lee

Yu-Lin Liu

Yu-Tsung Lin

Kuan-Cheng Liu

Jui-Pin Chang

A semiconductor device includes a semiconductor substrate, a circuit unit and an align mark. The circuit unit is disposed on the semiconductor substrate. The align mark includes a first part and a second part respectively formed in the semiconductor substrate and adjacent to two opposite sides of the circuit unit, wherein the first part and the second part depart from each other for a predetermined distance along with a first direction.

Semiconductor device and critical dimension defining method thereof

A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures.

Bit line structure, semiconductor device and method of forming the same

A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.

Non-volatile memory

A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

Memory and manufacturing method thereof

A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

Non-volatile memory and method of fabricating the same

A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed thereon and forming a patterned mask layer on the conductive layer. In addition, a portion of the conductive layer is removed by using the patterned mask layer as a mask and a spacer is formed on a sidewall of the patterned mask layer and the conductive layer. A portion of the conductive layer is removed until the material layer is exposed to form a conductive line, wherein the spacer and the patterned mask layer serve as a mask.

Method of fabricating conductive lines

An ultraviolet-programmable P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell to be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

UV-programmable P-type mask ROM

A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer and a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Non-volatile memory device and fabrication method thereof

A non-volatile memory capable of preventing the antenna effect and the fabrication thereof are described. The non-volatile memory includes a word-line having a high resistance portion and a memory cell portion on a substrate and a charge trapping layer located between the word-line and the substrate. The high resistance portion is electrically connected with a grounding doped region in the substrate and the memory cell portion is electrically connected with a metal interconnect over the substrate.

Non-volatile memory capable of preventing antenna effect and fabrication thereof

A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

A method for fabricating a Mask ROM is described, in which an ONO composite layer and a plurality of gate structures are formed on a substrate. A plurality of bit-lines are formed in the substrate between the gate structures and a plurality of word-lines are formed over the substrate to electrically connect with the gate structures. A chemical vapor deposition anti-reflective coating (CVD-ARC) with coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer not covered by the CVD-ARC. A plurality of plugs are then formed in the coding windows.

Mask read-only memory and fabrication thereof

A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

A method for fabricating an UV-programmed P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

UV-programmed P-type Mask ROM and fabrication thereof

A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.

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Chilung, Taiwan

Shou-Wei Huang