Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Mediatek Corporation

Shou-En Liu

Chun-Wei Chang

Jiaw-Ren Shih

Yung-Sheng Tsai

Bi-Ling Lin

Chung-Hsing Wang

Kuo-Nan Yang

Yu-Hsuan Lin

Chen-Pang Kung

Shyh-Horng Yang

Yung-Hui Yeh

Jhong-Sheng Wang

Chung-Kai Lin

Wei-Hsin Hou

Hsien-Sheng Huang

Tan-Li Chou

Wen-Sung Chiang

Lin-Chien Chen

Keng-Jui Chang

Ming-Han Hsieh

Ming-Tsung Lin

A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

Method and circuit for monitoring and controlling duty margin of a signal

A method includes identifying fingers of a first device and fingers of a second device. The method includes grouping the fingers of the first device into a first finger group and a second finger group, wherein the first finger group is electrically connected to the second finger group. The method further includes positioning the first finger group extends across a first doped region. The method further includes positioning the second finger group extends across a second doped region, wherein the second doped region has a same dopant type as the first doped region. The method further includes grouping the fingers of the second device into a third finger group and a fourth finger group, wherein the third finger group is electrically connected to the fourth finger group. The method further includes positioning the third finger group and the fourth finger group extending across the second doped region.

Circuit layout method

An interface circuit of an electronic device includes one or more pins, an internal circuit, an over-voltage protection circuit and a monitoring circuit. The pins are selectively connected to an external circuit. The over-voltage protection circuit is coupled between the internal circuit and at least one pin to prevent the internal circuit from being damaged by a voltage spike or a current surge received at the pin. The monitoring circuit is configured to monitor one or more electrical characteristics of at least one critical component in the internal circuit or the over-voltage protection circuit by monitoring the value of at least one parameter related to the electrical characteristics of the critical component. When the value of the parameter is outside of a safety range, the monitoring circuit outputs a warning signal.

Interface circuits to monitor and prevent overstress damage

A circuit layout includes a first device having a first set of fingers, wherein the first set of fingers is separated into a first finger group and a second finger group, the first finger group comprising a first number of fingers, and the second finger group comprising a second number of fingers. The circuit layout further includes a second device having a second set of fingers, wherein the second set of fingers includes a third finger group having a third number of fingers. The first finger group, the second finger group and the third finger group extend across a first doped region, and the third finger group is between the first finger group and the second finger group.

Circuit layout, layout method and system for implementing the method

A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.

Method of designing a circuit and system for implementing the method

A photosensor circuit including a first node, a level shifting circuit, a phototransistor and an inverter is provided. The first node has an operation voltage signal. The level shifting circuit is coupled to the first node for biasing the first node, so that the operation voltage signal is biased to an operation biasing level. The phototransistor is coupled to the first node for receiving an optical signal and accordingly generates a first electrical signal by means of controlling the level of the operation voltage signal. The inverter receives the first electrical signal and accordingly generates and outputs a second electrical signal, which indicates the intensity of the optical signal.

Photosensor circuit having a level shifting circuit for biasing a first node with an operation voltage signal and a phototransistor for modulating the level of the operation voltage signal

An intra-connection layout of array is disclosed. An alterable area is disposed between the devices of a device array. The alterable area includes an insulation layer, a plurality of first conductive wires and a plurality of second conductive wires. The first conductive wires are disposed within the alterable area along a first direction for selectively connecting electrical paths in the first direction between different devices. The second conductive wires are disposed within the alterable area along a second direction for selectively connecting electrical paths in the second direction between different devices. The insulation layer is disposed within the alterable area and between the above-mentioned first conductive wires and second conductive wires, wherein the insulation layer has an opening to allow one of the first conductive wires and one of the second conductive wires to be contacted with each other.

Intra-connection layout of array

Growing community of inventors

Hsinchu, Taiwan

Shou-En Liu