Matsushita Electronics Corporation

Shotaro Umebachi

Gota Kano

Kaname Motoyoshi

Katsushi Tara

Susumu Koike

Morio Inoue

Iwao Teramoto

Hiromitsu Takagi

Toshiharu Tambo

Hidetaka Hashimoto

This invention relates to a method of manufacturing an Arsenic-including compound semiconductor device comprising the steps of forming an ion implantation layer in a specified region of an As compound semiconductor wafer, forming an As layer on the surface of the wafer, and annealing the water. In this manner, As evaporation in the ion implantation layer by annealing heat may be prevented. Accordingly, sufficient substitution of the implanted ions and the ions other than As ions composing the As compound may be achieved, thereby preventing lowering of the electrical activation of the As compound semiconductor device. In addition, the electrical activation becomes uniform over the whole area of the water.

Method of manufacturing an arsenic-including compound semiconductor

A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:

Method of making FET utilizing shadow masking and diffusion from a doped

The invention discloses a heterojunction Type GaAs field-effect transistor of the type in which a channel region consists of an n-type GaAs layer with a higher mobility and a gate region consists of a p-type Ga.sub.1-y Al.sub.y As layer which is grown heteroepitaxially. The length of the gate is of the order of microns, and a gate, source and drain electrodes are self-aligned. The gate region is etched in the form of a mushroom with the use of an etchant which etched the GaAlAs layer and the Ga-As layer at different etching rates so that the gate, source and drain electrodes may be formed by only one vacuum deposition of a metal such as aluminum.

Junction gate type GaAs field-effect transistor and method of forming

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Kyoto, Japan

Shotaro Umebachi