Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Collabo Innovations, Inc.

Shota Nakashima

Atsuo Inoue

Akira Matsuzawa

Haruyasu Yamada

Takeshi Yamamoto

Joji Katsura

Tetsuro Yoshimoto

Miki Mizushima

Seizo Inagaki

Yuichiro Nakai

Rie Ito

Inoue Atsuo

Inagaki Seizo

When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the 'H' pulse of the second transmit signal to a signal advanced by time of tdrelative to the 'L' pulse of the first transmit signal when the logic of transmit data is &#x201c;1&#x201d;, and to a signal advanced by time of tdrelative thereto when the logic of transit data is &#x201c;0&#x201d; and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Two-wire type data communication method and system, controller and data recording apparatus

To provide a contactless communication system that can reduce a time required to complete an identification of all data carriers that exist around a reader/writer and thus attempt to speed up its processing. According to the contactless communication system, multiple data carriers detect a response requesting command from an access device and send back an individual response signal for one-bit information to the access device at a time that is ordered based on a portion of each carrier's identification information, and the access device monitors individual slots for the response signals and determines that detection of the presence of data carriers is completed when it has obtained individual signals from the data carriers, thereby reducing the time required to complete the identification of all data carriers.

Contactless communication system and data carrier used for the same

In a controller device, when a first transmitting signal is at a 'L' level, a first operation voltage is high and the amplitude of signals CK and ICK is large, and on the contrary, the amplitude is small when the first transmitting signal is at a 'H' level. In a data carrier device, the signals CK and ICK are subjected to full-wave rectification by a rectifier circuit so as to generate a second operation voltage, and a first receiving signal is extracted from the second operation voltage by a first signal detection circuit. On the other hand, in the data carrier device, when a second transmitting signal is at a &#x201c;L&#x201d; level, impedance between two contacts is small and the amplitude of the signals CK and ICK is small, and on the contrary, the amplitude is large when the second transmitting signal is at a &#x201c;H&#x201d; level. In the controller device, change of the amplitude of the signal ICK is extracted as a second receiving signal by a second signal detection circuit. Accordingly, supply of power and clock and two-way serial data communication can be simultaneously executed between the controller device and the data carrier device through merely two contacts.

Data communication system, controller device and data communication method

A state control circuit gives an inactive state control signal to a CPU and an active state control signal to a data transmission circuit. In response to this, the CPU goes into the halt state and the data transmission circuit goes into the receive state. When receive processing is completed, the state control circuit gives an active state control signal to the CPU. In response to this, the CPU restores from the halt state to the operative state. The CPU gives an instruction signal to the state control circuit. The state control circuit gives an inactive state control signal to the data transmission circuit. In response to this, the data transmission circuit goes into the halt state.

IC card

A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current is allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Dynamic BiCMOS logic gates

A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Growing community of inventors

Osaka, Japan

Shota Nakashima