Kabushiki Kaisha Toshiba

Shota Kitamura

Seiji Yamada

Memory cells each having a floating gate ( ), control gate ( ), and source and drain diffusion layers ( ) are formed on a silicon substrate ( ). A silicon nitride film ( ) by low-pressure CVD is maintained as side wall insulating films on side walls of the gates in each memory cell. A silicon nitride film ( ) by plasma CVD is formed to cover a memory cell array, and silicon oxide films ( ) are made on the silicon nitride film ( ) to form an inter-layer insulating film. A common source line ( ) connected to the source diffusion layer is formed to embed in the silicon oxide film ( ), and a bit line ( ) connected to the drain diffusion layer ( ) is formed on the silicon oxide film ( ).

Growing community of inventors

Kawasaki, Japan

Shota Kitamura