Fujitsu Corporation

Shosuke Mori

Kiminori Fujisaku

Makoto Awaga

Hitoshi Ono

Atsushi Sakurai

Mitsuru Yamauchi

Tatsuya Suzuki

Satoshi Aoki

A multiprocessor system used, for example, in a personal computer, wherein different types of microprocessors are used independently of the architecture of each microprocessor. The system includes a control register, a control circuit, and a common peripheral circuit mounted, for example, on a main board, and a plurality of kinds of microprocessors each mounted, for example, on a sub-board connected to the main board. The control circuit transmits a halt request signal to a first microprocessor which is currently operating, in response to coincidence between an output signal of the control register and the status signal indicating that a second microprocessor is in a halt condition, when the output signal of the control register is changed by the first microprocessor. Then, the control circuit releases a halt request signal applied to the second microprocessor in response to coincidence between a status signal indicating that the first microprocessor has entered into a halt condition and the output signal of the control register.

Multiprocessor system

A display system comprises a first image memory storing first image data, a second image memory storing second image data operable independently from the first image memory, a display selection and combination circuit, and two display units. The display selection and combination circuit connected to the first and second image memories is formed such that each of the display units displays a combination of data from the image memories according to a display request. Normally, the display units are cathode ray tubes or liquid crystal displays. Usually, one of the first and second image memories stores character information, such as letters and numerals, and the other stores graphic information, such as figures and curves.

Combined graphic and textual display system

An information processor with a read only memory ROM stores a plurality of initial program loader (IPL) programs. The ROM memory has address inputs divided into two parts used to access each IPL program. One part of the address inputs of the ROM memory is connected to an address bus from a central processing unit (CPU) in order to be used to access the contents of one of the programs. The other part of the address inputs of said ROM memory is connected to an IPL setting part or switching which sets or selects a desired one of said plurality of IPL programs. The IPL setting part includes a plurality of switches connected to upper bit terminals of the ROM address inputs.

Processor having plural initial loading programs for loading different

A data processing apparatus includes a CPU, a memory, and logic operation hardware. When a predetermined instruction code is identified, the logic operation hardware executes an arithmetic operation using data stored in the memory, while the CPU processes the same data. The logic operation hardware then writes the result of the arithmetic operation instead of the data processed by the CPU.

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Tokyo, Japan

Shosuke Mori