Fujitsu Corporation

Shosaku Yamasaki

Shigeo Tani

Mitsuhiro Kawaguchi

Hideki Matsui

Takashi Umegaki

Masao Nakano

Hiroyuki Matsuo

Atsuki Taniguchi

Kazuo Takatsu

Takeshi Toyoyama

Shigehisa Sakahara

Koji Komatsu

Ryoji Azumi

Toshiaki Kinoshita

Yoshimasa Itsuki

There is provided a time slot interchanger for processing channel setting data functioning as control data for interchanging time slots of multiplexed transmission data. In the time slot interchanger, processing of the channel setting data based on alarm data is performed in accordance with a preset first transmission capacity, and with respect to the channel setting data in accordance with a preset second transmission capacity, processing of the channel setting data in accordance with the first transmission capacity is dispersedly performed in a time series manner.

Time slot interchanger

In a transmission apparatus, unlike in the conventional transmission apparatus, a protection switch is not arranged on the signal path, but a TSI having only the basic function performs the function of the protection switch as a substitute, a processing unit to perform the switching function at a low rate is artificially constructed on a TSI, the switch process of SONET protection type is artificially executed by the TSI, and a signal for controlling the TSI function is further controlled thereby to realize the protection switch function. The logic of switching at the main signal rate in addition to the conventional TSI function is deleted.

Transmission apparatus

A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.

Network apparatus that determines whether data is written into buffer based on detection of a memory error

A transmission device performing prescribed processing on signals of a plurality of channels and transmitting the signals of the plurality of channels. The device includes a first storage unit for storing, in different memory cells for each channel, first control data in which one or more types of control data elements for each channel are configured as at least one word data; a first data structure conversion unit for selecting control data elements of the same type from the first control data of the plurality of channels stored in the first storage unit, and converting the structure of the first control data such that the control data elements of the same type are configured as one word data; and a data generation unit for processing, in word units, the first control data after conversion by the first data structure conversion unit, and generating second control data necessary for the prescribed processing.

Transmission device for processing and transmitting signals of a plurality of channels

An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.

Terminal relay device and relay method

A clock anomaly detection circuit includes: a dividing unit configured to output a divided target clock by dividing frequency of a target clock; a first time width measurement unit configured to obtain values of the divided target clock using rising edges of a monitoring clock that is synchronized with the target clock, and to measure an H level time with and an L level time width; a second time width measurement unit configured to obtain values of the divided target clock using falling edges of the monitoring clock, and to measure an H level time with and an L level time width; and an anomaly determination unit configured to determine that the target clock is abnormal when an anomaly is detected in the H level time width or the L level time width measured in the first time width measurement unit and when an anomaly is detected in the H level time width or the L level time width measured in the second time width measurement unit.

Clock anomaly detection circuit and clock anomaly detection method

In an SDH transmission apparatus, an intra-apparatus reference frame timing produced by a main signal processing unit (A/B) which accommodates a plurality of interface units () is distributed to the interface units () by a frame timing production section (-) to suppress displacements of the frame top positions of the main signals from the IF boards to the minimum, whereby frame timing re-clocking of the main signals is performed with the least necessary memory capacity without using a pointer processing technique so that, even if the number of channels to be processed increases, the apparatus scale can be suppressed to the minimum.

SDH transmission apparatus and frame timing re-clocking method for SDH transmission apparatus

A connection switching circuit is disposed in each node of a ring system in which a first ring and a second ring are provided with two communication lines which allow data to flow in a different direction respectively and is connected with a currently used passage and preliminary passage. The connection switching circuit comprises an alarm correction reading part for generating a control signal, an alarm monitor part for outputting respective alarm detection signals, a currently used/and preliminary alarm recognition part, and a switching control signal generation part for generating a control signal for selecting a passage, wherein either the currently used passage or the preliminary passage is selected by monitoring the alarm of the data which flows on the currently used passage or the preliminary passage to connect the first ring and the second ring with each other.

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Kawasaki, Japan

Shosaku Yamasaki