Hitachi, Ltd.

Other

Shosaku Ishihara

Koji Suzuki

Masahide Okamoto

Mutsumi Horikoshi

Akihiro Yasuda

Norihiro Ami

Shiro Yamashita

Hideto Yoshinari

Takashi Kuroki

Shinji Hiramitsu

Shinichi Fujiwara

Satoshi Matsuyoshi

Ryouichi Kajiwara

Osamu Ikeda

Masahide Harada

Koji Sasaki

Isamu Yoshida

Akio Yasukawa

Gyozo Toda

Mitsuhiro Oshiki

Masato Nakamura

Tadaaki Kariya

Mikio Izumi

Tatsuji Sakamoto

Shuzou Sano

Takaya Osawa

To prevent any uneven solder wetting in a main surface of electrodes of a semiconductor connected with a main surface of a planar lead and any displacement of the lead vis-a-vis the electrodes due to the reflow of the solder in a semiconductor module having the semiconductor element mounted on a substrate and the planar lead electrically connected therewith, the present invention provides an improved semiconductor module characterized in that the width of at least a part of the region of the main surface of the lead facing the semiconductor element is expanded wider than or equal to the width of the electrodes formed on the semiconductor element, and preferably the other part of the main surface of the lead soldered to an electrode formed on the substrate is split in the extending direction thereof.

Power semiconductor module with MOS chip

A semiconductor module of the present invention comprises a first conductive layer (film) and a second conductive layer (film) which are separately formed on the main surface of a packed substrate, a thermal diffusion plate connected by solder to the upper surface of the first conductive layer, a semiconductor element connected by solder to the upper surface of the thermal diffusion plate, and a lead having one end connected by solder to the second conductive layer and the other end connected by solder to the semiconductor element, wherein the outer periphery of the connected region where the semiconductor element is connected by solder to the upper surface of the thermal diffusion plate is formed with protrusion parts protruding up from the connecting region and a turning of the semiconductor element in the upper surface of the thermal diffusion plate in the solder connecting process is suppressed by the protrusion parts.

Power semiconductor module

The present invention provides a semiconductor device comprising a semiconductor element and a copper member which are bonded to each other by a bismuth-based (Bi-based) bonding material having its melting temperature of not less than 250&#xb0; C., wherein silver (Ag) is diffused in a region of the bonding material in the vicinity of an interface thereof to the semiconductor element with an inclination of concentration of the silver from the interface, in order to realize a manufacture of the semiconductor device without using lead (Pb) at low cost.

Semiconductor device

A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3&#xd7;10&#x2212;6/&#xb0; C. to 8&#xd7;10&#x2212;6/&#xb0; C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250&#xb0; C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250&#xb0; C.

In order to provide a two-dimensionally arrayed probe (element packaging structure) in which a multilayer element can be used as a piezoelectric ceramic transducer element, each defective element can be replaced and the ill connection of each element can be repaired, and in order to provide a multilayer electric part suitable for realizing such an element packaging structure, the multilayer electronic part is configured with a multilayer chip-like element having a surface electrode, an internal electrode and a back electrode on the one hand and a flexible board attached to one side surface of the chip-like element on the other hand, alternate ones of the electrodes along the multilayer of the chip-like element are connected electrically to each other by the electrode pattern of the flexible board thereby to form two electrode groups, and the end portions of the electrode pattern of the flexible board are used as the two electrode portions for external connection which are electrically connected to the two electrode groups.

Multilayer electronic part, its manufacturing method, two-dimensionally arrayed element packaging structure, and its manufacturing method

A via interconnection of a glass-ceramic wiring board is made by blending a copper powder to a vehicle including a cellulose derivative, adding a metal oxide powder having a mean particle diameter of from at least 1 &mgr;m to at most 4 &mgr;m to the vehicle and blending them, adjusting the viscosity of the vehicle by adding the cellulose derivative and filling them to a via; and sintering the via at a temperature of at least 900&deg; C. to at most 1060&deg; C., and forming the via interconnection.

Method of manufacturing via interconnection of glass-ceramic wiring board

A glass-ceramic wiring board includes an insulating substrate, a via disposed in the insulating substrate and a via interconnection filling the interior of the via. The via interconnection is sintered material having metal particles. The metal particles have a cross-sectional area per one metal particle surrounded by a metal particle boundary of less than 2000 &mgr; , which can be determined by cutting, etching and examining a cross-section of the via.

Glass-ceramic wiring board

In a ceramic wiring board which comprises a copper via, breaks and defects of via interconnections resulting from enlargement of copper particles in the interior of the via during sintering, are prevented. For this purpose, alumina of mean particle diameter from 1 &mgr;m to 4 &mgr;m is disposed in the interior of the via interconnection after sintering at an average interval of 7.4 &mgr;m or less.

Ceramics substrate with electronic circuit and its manufacturing method

A ceramic multilayer wiring board is provided in which ceramic insulating layers and wiring patterns provided thereon are connected by conductors filling through-holes formed in the ceramic insulating layers. The through-holes are so formed that the superficial portions of each through-hole of the ceramic multilayer wiring board is smaller in diameter than the inside portion of the through-hole between the superficial portion. This can prevent the board from being cracked around the through-holes.

Ceramic multilayer wiring board

Growing community of inventors

Chigasaki, Japan

Shosaku Ishihara